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1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright 2003, zarlink semiconductor inc. all rights reserved. features ? 8 gigabit ports with gmii and pcs interface - gigabit port can also support 100/10 mbps mii interface - provide hot plug support for gmii/pcs module - 2 gigabit ports can be aggregated into 2gbps stacking port working with vtx2600 in stacking mode ? high performance layer 2 packet forwarding (11.904m packets per second) and filtering at full-wire speed ? maximum throughput is 8 gbps non-blocking ? centralized shared-memory architecture ? consists of two memory domains at 133 mhz - frame buffer domain: two banks of zbt-sram with 2m/4mb total - switch database domain with 256k/512k sram ? up to 64k mac addresses to provide large node aggregation in wiring closet switches ? provides port based and id tagged vlan (ieee802.1q) up to 4k vlan ? support ip multicast with igmp snooping up to 64k groups. ? traffic classification ? classify traffic into 8 transmission priorities per port ? supports delay bounded, strict priority, and wfq ? provides 2 level dropping precedence with wred mechanism - user controlled thresholds for wred ? classification based on layer 2, 3 markings - vlan priority field in vlan tagged frame - ds/tos field in ip packet ? the precedence of above two classifications can be programmable october 2003 ordering information MVTX2804Ag 596 pin hsbga -40 c to +85 c mvtx2804 8-port 1000 mbps ethernet distributed switch data sheet figure 1 - MVTX2804Ag functional block diagram frame data buffer a zbt-sram (1m/2mb) frame data buffer b zbt-sram (1m/2mb) sram 256/512k sw database mac table frame engine scheduler fdb interface sdb interface search engine 64bit 64bit 32bit nm database gmii /pcs port 0 gmii /pcs port 1 gmii /pcs port 2 gmii /pcs port 3 gmii /pcs port 4 gmii /pcs port 5 gmii /pcs port 6 gmii /pcs port 7 16/8bit- bus/ serial management module cpu vtx2804 led
mvtx2804 data sheet 2 zarlink semiconductor inc. qos support description the mvtx2800ag family is a group of 8-port 1000 mbps non-blocking ethernet switch chips with on-chip address memory. a single chip provides a maximum of eight 1000 mbps ports and a dedicated cpu interface with a 16/8-bit bus for managed and unmanaged switch applications. the vt x2800 family consists of the following four products: ? vtx2804 8 gigabit ports managed ? vtx2803 8 gigabit ports unmanaged ? vtx2802 4 gigabit ports managed ? vtx2801 4 gigabit ports unmanaged the MVTX2804Ag supports up to 64k mac addresses to aggr egate traffic from multiple wiring closet stacks. the centralized shared-memory architecture allows a very hi gh performance packet-forwarding rate of 11.904m packets per second at full wire speed. the chip is optimized to provide a low-cost, high performance workgroup, and wiring closet, layer 2 switching solution with 8 gigabit ethernet ports. two frame buffer memory domains utiliz e cost effective, high-performance zbt-sram with aggregated bandwidth of 16gbps to support full wire speed on all external ports simultaneously. with strict priority, delay bounded, and wrr transmis sion scheduling, plus wred memory congestion scheme, the chip provides powerful qos functions for convergent network multimedia and mission-critical applications. the chip provides 8 transmission priorities and 2 level drop pr ecedence. traffic is assigned its transmission priority and dropping precedence based on the frame vlan tag priority or ds/tos fields in ip packets. ip multicast snooping prov ides up to 64k simult aneous ip multicast groups. with 4k ieee 802.1q vlans, the MVTX2804Ag provides th e ability to logically group users to control multicast traffic. ? supports ieee 802.1p/q quality of service with 8 priority ? buffer management: reserve buffers on per class and per port basis ? port-based priority: vlan priority with tagged frame can be overwritten by the priority of pvid ? qos features can be configured on a per port basis ? packet filtering and port security ? static addressing filtering for source and/or destination mac address ? static learned mac addresses will not be aged out ? secure mode per port: prevent learning for port in a secure mode ? support per mac per port filtering ? full duplex ethernet ie ee 802.3x flow control ? provides ethernet multicast and broadcast control ? 4 port trunking groups, 8 ports per group (trunking can be based on source mac and/or destination mac and source port) ? led signals provided by a serial or parallel interface ? cpu interface supports 16/8-bit cpu bus in managed mode and a synchronous serial interface and i 2 c interface in unmanaged mode ? snmp/rmon support with cpu ? built-in mib counter ? spanning tree with cpu ? multiple spanning trees (per spanning tree per vlan) ? hardware auto-negotiation through serial management interface (mdio) for gigabit ethernet ports, supports 10/100/1000 mbps ? bist for internal and external sram-zbt ?i 2 c eeprom or synchronous serial port for configuration ? packaged in 596-pin bga
mvtx2804 data sheet 3 zarlink semiconductor inc. the MVTX2804Ag supp orts port trunking/load sharin g on the 1000 mbps ports with fail-over capability. the port trunking/load sharing can be used to group ports between interlinked switches to increase the effective network bandwidth. in full-duplex mode, ieee 802.3x flow control is provided. the physical codi ng sublayer (pcs) is integrated on- chip to provide a direct 10-bit gmii interface, or the pcs can be bypassed to provide an interface to existing fiber- based gigabit ethernet transceivers. statistical information for etherstat snmp and remote m onitoring management information base (rmon mib) are collected independently for each of the ei ght ports. access to these statistical counter/registers is provided via the cpu interface. snmp management frames can be receiv ed and transmitted via the cpu interface, creating a complete network management solution. the MVTX2804Ag is fabricated using 0.25mm technology. i nputs, however, are 3.3v tolerant and the outputs are capable of directly interfacing to lvttl levels. the MVTX2804Ag is packaged in a 596-pin ball grid array package.
mvtx2804 data sheet table of contents 4 zarlink semiconductor inc. 1.0 block functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.1 frame data buffer (fdb) interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.2 switch database (sdb) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.3 gmii/pcs mac module (gmac) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.4 cpu interface module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.5 management module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.6 frame engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.7 search engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.8 led interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.9 internal memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.0 system configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.1 management and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2 managed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3 register configuration, frame transmission, and frame rece ption . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3.1 ethernet frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3.2 control frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.4 unmanaged mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.5 i 2 c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.5.1 start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.5.2 address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.5.3 data direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.5.4 acknowledgment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.5.5 data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.5.6 stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.6 synchronous serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.6.1 write command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.6.2 read command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.0 data forwarding protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.1 unicast data frame forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.2 multicast data frame forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.3 frame forwarding to and from cpu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.0 memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.2 detailed memory information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.0 search engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.1 search engine overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.2 basic flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.3 search, learning, and aging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.3.1 mac search. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.3.2 learning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.3.3 aging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.3.4 data structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.3.5 vlan port association table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.0 frame engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.1 data forwarding summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.2 frame engine details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.2.1 fcb manager. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.2.2 rx interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.2.3 rxdma. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.2.4 txq manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.3 port control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.4 txdma. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
mvtx2804 data sheet table of contents 5 zarlink semiconductor inc. 7.0 quality of service and flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.1 model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.2 four qos configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.3 delay bound . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.4 strict priority and best effort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.5 weighted fair queuing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.6 shaper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.7 wred drop threshold management support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.8 buffer management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.8.1 dropping when buffers are scarce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.9.1 unicast flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.9.2 multicast flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.10 mapping to ietf diffserv classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.0 port trunking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.1 features and restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.2 unicast packet forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.3 multicast packet forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.4 preventing multicast packets from looping back to the source trunk. . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9.0 led interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9.2 serial mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9.3 parallel mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.4 led control registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 10.0 hardware statistics counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 10.1 hardware statistics counters list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 10.2 ieee 802.3 hub management (r fc 1213) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 10.2.1 event counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 10.2.1.1 readableoctet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 10.2.1.2 readableframe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 10.2.1.3 fcserrors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 10.2.1.4 alignmenterrors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 10.2.1.5 frametoolongs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 10.2.1.6 shortevents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 10.2.1.7 runts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 10.2.1.8 collisions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 10.2.1.9 lateevents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 10.2.1.10 verylongevents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 10.2.1.11 dataratemisatches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1 10.2.1.12 autopartitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 10.2.1.13 totalerrors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10.3 ieee - 802.1 bridge ma nagement (rfc 1286) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10.3.0.1 event counters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10.3.0.3 outframes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10.3.0.4 indiscards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10.3.0.5 delayexceededdiscards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10.3.0.6 mtuexceededdiscards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10.4 rmon - ethernet statistic group (rfc 1757) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10.4.1 event counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10.4.1.1 drop events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10.4.1.2 octets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 10.4.1.3 broadcastpkts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 10.4.1.4 multicastpkts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
mvtx2804 data sheet table of contents 6 zarlink semiconductor inc. 10.4.1.5 crcalignerrors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 10.4.1.6 undersizepkts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 10.4.1.7 oversizepkts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 10.4.1.8 fragments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 10.4.1.9 jabbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 10.4.1.10 collisions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 10.4.1.11 packet count for different size groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 11.0 register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 11.1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 11.2 directly accessed registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 11.2.1 index_reg0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 11.2.2 index_reg1 (only needed for cpu 8-bit bus mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 11.2.3 data_frame_reg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 11.2.4 control_frame_reg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 11.2.5 command & status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 11.2.6 interrupt register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 11.2.7 control frame buffer1 ac cess register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 11.2.8 control frame buffer2 ac cess register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 11.3 group 0 address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 11.3.1 mac ports group. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 11.3.1.1 ecr1pn: port n control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 11.3.1.2 ecr2pn: port n control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 11.3.1.3 ecrmisc1 - cpu po rt control register misc1 . . . . . . . . . . . . . . . . . . . . . . . . . . 55 11.3.1.4 ecrmisc2 - cpu po rt control register misc2 . . . . . . . . . . . . . . . . . . . . . . . . . . 55 11.3.1.5 ggcontrol 0- extra giga port control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 11.3.1.6 ggcontrol 1- extra giga port control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 11.3.1.7 ggcontrol 2- extra giga port control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 11.3.1.8 ggcontrol 3- extra giga port control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 11.4 group 1 address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 11.4.1 vlan group. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 11.4.1.1 avtcl - vlan type code register low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 11.4.1.2 avtch - vlan type co de register high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 11.4.1.3 pvmap00_0 - port 00 configuration register 0 . . . . . . . . . . . . . . . . . . . . . . . . . 58 11.4.1.4 pvmap00_1 - port 00 configuration register 1 . . . . . . . . . . . . . . . . . . . . . . . . . 58 11.4.1.5 pvmap00_3 - port 00 configuration register 3 . . . . . . . . . . . . . . . . . . . . . . . . . 59 11.5 port vlan map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 11.5.1 pvmode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 11.6 group 2 address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 11.6.1 port trunking group. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 11.6.1.1 trunk0 - trunk group 0 member (managed mode only) . . . . . . . . . . . . . . . . . 61 11.6.1.2 trunk1 - trunk group 1 member (managed mode only) . . . . . . . . . . . . . . . . . 61 11.6.1.3 trunk2- trunk group 2 me mber (managed mode only) . . . . . . . . . . . . . . . . . 61 11.6.1.4 trunk3- trunk group 3 me mber (managed mode only) . . . . . . . . . . . . . . . . . 62 11.6.1.5 trunk_hash_mode - trunk hash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 11.6.1.6 trunk0_mode - trunk group 0 mode (unm anaged mode) . . . . . . . . . . . . . . . . 62 11.6.1.7 trunk0_hash0 - trunk group 0 hash result 0,1,2 destination port number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 11.6.1.8 trunk0_hash1 - trunk group 0 hash result 2,3,4,5 destination port number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 11.6.1.9 trunk0_hash2 - trunk group 0 hash result 5,6,7 destination port number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 11.6.1.10 trunk0_hash3 - trunk group 0 h ash result 8,9,10 destination port
mvtx2804 data sheet table of contents 7 zarlink semiconductor inc. number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 11.6.1.11 trunk0_hash4 - trunk group 0 hash result 10,11,12,1 3 destination port number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 11.6.1.12 trunk0_hash5 - trunk group 0 h ash result 13,14,15 destination port number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 11.6.1.13 trunk1_mode - trunk group 1 mode (unm anaged mode) . . . . . . . . . . . . . . . 64 11.6.1.14 trunk1_hash0 - trunk group 1 hash result 0, 1, 2 destination port number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 11.6.1.15 trunk1_hash1 - trunk group 1 hash result 2, 3, 4, 5 destination port number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 11.6.1.16 trunk1_hash2 - trunk group 1 hash result 5, 6, 7 destination port number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 11.6.1.17 trunk1_hash3 - trunk group 1 h ash result 8, 9, 10 destination port number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 11.6.1.18 trunk1_hash4- trunk group 1 ha sh result 11, 12, 13 destination port number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 11.6.1.19 trunk1_hash5 - trunk group 1 hash result 13, 14, 15 destination port number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 11.6.1.20 trunk2_hash0 - trunk group 2 hash result 0, 1, 2 destination port number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 11.6.1.21 trunk2_hash1 - trunk group 2 hash result 2, 3, 4, 5 destination port number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 11.6.1.22 trunk2_hash2 - trunk group 2 hash result 5, 6, 7 destination port number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 11.6.1.23 trunk2_hash3 - trunk group 2 h ash result 8, 9, 10 destination port number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 11.6.1.24 trunk0_hash3 - trunk group 0 h ash result 8,9,10 destination port number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 11.6.1.25 trunk0_hash4 - trunk group 0 hash result 10,11,12,1 3 destination port number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 11.6.1.26 trunk0_hash5 - trunk group 0 h ash result 13,14,15 destination port number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 11.6.1.27 trunk1_mode - trunk group 1 mode (unm anaged mode) . . . . . . . . . . . . . . . 67 11.6.1.28 trunk1_hash0 - trunk group 1 hash result 0, 1, 2 destination port number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 11.6.1.29 trunk1_hash1 - trunk group 1 hash result 2, 3, 4, 5 destination port number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 11.6.1.30 trunk1_hash2 - trunk group 1 hash result 5, 6, 7 destination port number68 11.6.1.31 trunk1_hash3 - trunk group 1 h ash result 8, 9, 10 destination port number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 11.6.1.32 trunk1_hash4- trunk group 1 ha sh result 11, 12, 13 destination port number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 11.6.1.33 trunk1_hash5 - trunk group 1 hash result 13, 14, 15 destination port number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 11.6.1.34 trunk2_hash0 - trunk group 2 hash result 0, 1, 2 destination port number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 11.6.1.35 trunk2_hash1 - trunk group 2 hash result 2, 3, 4, 5 destination port number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 11.6.1.36 trunk2_hash2 - trunk group 2 hash result 5, 6, 7 destination port number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 11.6.1.37 trunk2_hash3 - trunk group 2 h ash result 8, 9, 10 destination port
mvtx2804 data sheet table of contents 8 zarlink semiconductor inc. number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 11.6.1.38 trunk2_hash4 - trunk group 2 hash result 10, 11, 12, 13 destination port number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 11.6.1.39 trunk2_hash5 - trunk group 2 hash result 13, 14, 15 destination port number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 11.6.1.40 trunk3_hash0 - trunk group 3 hash result 0, 1, 2 destination port number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 11.6.1.41 trunk3_hash1 - trunk group 3 hash result 2, 3, 4, 5 destination port number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 11.6.1.42 trunk3_hash2 - trunk group 3 hash result 5, 6, 7 destination port number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 11.6.1.43 trunk3_hash3 - trunk group 3 h ash result 8, 9, 10 destination port number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 11.6.1.44 trunk3_hash4 - trunk group 3 hash result 10, 11, 12, 13 destination port number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 11.6.1.45 trunk3_hash5 - trunk group 3 hash result 13, 14, 15 destination port number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 11.6.2 multicast hash registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 11.6.2.1 multicast_hash00 - multicast hash r esult0 mask byte [7:0] . . . . . . . . . . . . 71 11.6.2.2 multicast_hash01 - multicast hash r esult1 mask byte [7:0] . . . . . . . . . . . . 71 11.6.2.3 multicast_hash02 - multicast hash r esult2 mask byte [7:0] . . . . . . . . . . . . 71 11.6.2.4 multicast_hash03 - multicast hash r esult3 mask byte [7:0] . . . . . . . . . . . . 72 11.6.2.5 multicast_hash04 - multicast hash r esult4 mask byte [7:0] . . . . . . . . . . . . 72 11.6.2.6 multicast_hash05 - multicast hash r esult5 mask byte [7:0] . . . . . . . . . . . . 72 11.6.2.7 multicast_hash06 - multicast hash r esult6 mask byte [7:0] . . . . . . . . . . . . 72 11.6.2.8 multicast_hash07 - multicast hash r esult7 mask byte [7:0] . . . . . . . . . . . . 72 11.6.2.9 multicast_hash08 - multicast hash r esult8 mask byte [7:0] . . . . . . . . . . . . 72 11.6.2.10 multicast_hash09 - mult icast hash result9 mask byte [7 :0] . . . . . . . . . . . 72 11.6.2.11 multicast_hash10 - mult icast hash result10 mask byte [7:0] . . . . . . . . . . 72 11.6.2.12 multicast_hash11 - mult icast hash result11 mask byte [7:0] . . . . . . . . . . 73 11.6.2.13 multicast_hash12 - mult icast hash result12 mask byte [7:0] . . . . . . . . . . 73 11.6.2.14 multicast_hash13 - mult icast hash result13 mask byte [7:0] . . . . . . . . . . 73 11.6.2.15 multicast_hash14 - mult icast hash result14 mask byte [7:0] . . . . . . . . . . 73 11.6.2.16 multicast_hash15 - mult icast hash result15 mask byte [7:0] . . . . . . . . . . 73 11.6.2.17 multicast_hashml - multicast hash bit[ 8] for result7-0 . . . . . . . . . . . . . . 73 11.6.2.18 multicast_hashml - multicast hash bit[ 8] for result 15-8 . . . . . . . . . . . . . 73 11.7 group 3 address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 11.7.1 cpu port configuration group. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 11.7.1.1 mac0 - cpu mac address byte 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 11.7.1.2 mac1 - cpu mac address byte 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 11.7.1.3 mac2 - cpu mac address byte 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 11.7.1.4 mac3 - cpu mac address byte 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 11.7.1.5 mac4 - cpu mac address byte 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 11.7.1.6 mac5 - cpu mac address byte 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 11.7.1.7 int_mask0 - interrupt mask 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 11.7.1.8 int_mask1 - interrupt mask 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 11.7.1.9 int_status0 - masked interrupt status regi ster0 . . . . . . . . . . . . . . . . . . . . . 75 11.7.1.10 int_status1 - masked interrupt status re gister1 . . . . . . . . . . . . . . . . . . . . 75 11.7.1.11 intp_mask0 - interrupt mask for mac port 0,1 . . . . . . . . . . . . . . . . . . . . . . . . 76 11.7.1.12 intp_mask1 - interrupt mask for mac port 2,3 . . . . . . . . . . . . . . . . . . . . . . . . 76 11.7.1.13 intp_mask4 - interrupt mask for mac port 4,5 . . . . . . . . . . . . . . . . . . . . . . . . 76 11.7.1.14 intp_mask5 - interrupt mask for mac port 6,7 . . . . . . . . . . . . . . . . . . . . . . . . 77
mvtx2804 data sheet table of contents 9 zarlink semiconductor inc. 11.7.2 rqs - receive queue select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 11.7.3 rqss - receive queue status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 11.7.4 tx_age - tx queue aging timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 11.8 group 4 address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 11.8.1 search engine group. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 11.8.1.1 agetime_low - mac address aging time low . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 11.8.1.2 agetime_high -mac address aging time high . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 11.8.1.3 v_agetime - vlan to port aging time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 11.8.1.4 se_opmode - search engine operation mode . . . . . . . . . . . . . . . . . . . . . . . . . . 79 11.8.1.5 scan - scan control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 11.9 group 5 address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 11.9.1 buffer cont rol/qos group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 11.9.1.1 fcbat - fcb aging timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 11.9.1.2 qosc - qos control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 11.9.1.3 fcr - flooding cont rol register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 11.9.1.4 avpml - vlan priority map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 11.9.1.5 avpmm - vlan priority map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 11.9.1.6 avpmh - vlan priority map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 11.9.1.7 tospml - tos priority map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 11.9.1.8 tospmm - tos priority map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 11.9.1.9 tospmh - tos priority map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 11.9.1.10 avdm - vlan discard map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 11.9.1.11 tosdml - tos discard map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 11.9.2 bmrc - broadca st/multicast rate control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 11.9.3 ucc - unicast congestion control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 11.9.4 mcc - multicast congestion control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 11.9.5 prg - port re servation for giga ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 11.9.6 fcb reservation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 11.9.6.1 sfcb - share fcb size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 11.9.6.2 c2rs - class 2 reserved size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 11.9.6.3 c3rs - class 3 reserved size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 11.9.6.4 c4rs - class 4 reserved size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 11.9.6.5 c5rs - class 5 reserved size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 11.9.6.6 c6rs - class 6 reserved size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 11.9.6.7 c7rs - class 7 reserved size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 11.9.7 classes byte gigabit port 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 11.9.7.1 qosc00 - byte_c2_g0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 11.9.7.2 qosc01 - byte_c3_g0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 11.9.7.3 qosc02 - byte_c4_g0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 11.9.7.4 qosc03 - byte_c5_g0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 11.9.7.5 qosc04 - byte_c6_g0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 11.9.7.6 qosc05 - byte_c7_g0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 11.9.8 classes byte gigabit port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 11.9.8.1 qosc06 - byte_c2_g1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 11.9.8.2 qosc07 - byte_c3_g1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 11.9.8.3 qosc08 - byte_c4_g1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 11.9.8.4 qosc09 - byte_c5_g1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 11.9.8.5 qosc0a - byte_c6_g1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 11.9.8.6 qosc0b - byte_c7_g1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 11.9.9 classes byte gigabit port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 11.9.9.1 qosc0c - byte_c2_g2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 11.9.9.2 qosc0d - byte_c3_g2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
mvtx2804 data sheet table of contents 10 zarlink semiconductor inc. 11.9.9.3 qosc0e - byte_c4_g2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 11.9.9.4 qosc0f - byte_c5_g2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 11.9.9.5 qosc10 - byte_c6_g2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 11.9.9.6 qosc11 - byte_c7_g2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 11.9.10 classes byte gigabit port 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 11.9.10.1 qosc12 - byte_c2_g3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 11.9.10.2 qosc13 - byte_c3_g3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 11.9.10.3 qosc14 - byte_c4_g3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 11.9.10.4 qosc15 - byte_c5_g3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 11.9.10.5 qosc16 - byte_c6_g3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 11.9.10.6 qosc17 - byte_c7_g3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 11.9.11 classes byte gigabit port 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 11.9.11.1 qosc18 - byte_c2_g4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 11.9.11.2 qosc019 - byte_c3_g4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 11.9.11.3 qosc1a - byte_c4_g4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 11.9.11.4 qosc1b - byte_c5_g4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 11.9.11.5 qosc1c - byte_c6_g4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 11.9.11.6 qosc1d- byte_c7_g4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 11.9.12 classes byte gigabit port 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 11.9.12.1 qosc1e- byte_c2_g5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 11.9.12.2 qosc1f - byte_c3_g5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 11.9.12.3 qosc20 - byte_c4_g5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 11.9.12.4 qosc21 - byte_c5_g5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 11.9.12.5 qosc22 - byte_c6_g5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 11.9.12.6 qosc23 - byte_c7_g5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 11.9.13 classes byte gigabit port 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 11.9.13.1 qosc24 - byte_c2_g6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 11.9.13.2 qosc25 - byte_c3_g6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 11.9.13.3 qosc26 - byte_c4_g6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 11.9.13.4 qosc27 - byte_c5_g6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 11.9.13.5 qosc28 - byte_c6_g6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 11.9.13.6 qosc29 - byte_c7_g6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 11.9.14 classes byte gigabit port 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 11.9.14.1 qosc2a - byte_c2_g7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 11.9.14.2 qosc2b - byte_c3_g7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 11.9.14.3 qosc2c - byte_c4_g7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 11.9.14.4 1qosc2d - byte_c5_g7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 11.9.14.5 qosc2e - byte_c6_g7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 11.9.14.6 qosc2f - byte_c7_g7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 11.9.15 classes byte limit cpu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 11.9.15.1 qosc30 - byte_c01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 11.9.15.2 qosc31 - byte_c02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 11.9.15.3 qosc32 - byte_c03 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 11.9.16 classes wfq credit set 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 11.9.16.1 qosc33 - credit_c0_g0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6 11.9.16.2 qosc34 - credit_c1_g0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6 11.9.16.3 qosc35 - credit_c2_g0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7 11.9.16.4 qosc36 - credit_c3_g0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7 11.9.16.5 qosc37 - credit_c4_g0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7 11.9.16.6 qosc38 - credit_c5_g0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7 11.9.16.7 qosc39- credit_c6_g0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7 11.9.16.8 qosc3a- credit_c7_g0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7
mvtx2804 data sheet table of contents 11 zarlink semiconductor inc. 11.9.17 classes wfq credit port g1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 11.9.17.1 qosc3b - credit_c0_g1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 8 11.9.17.2 qosc3c - credit_c1_g1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 11.9.17.3 qosc3d - credit_c2_g1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 11.9.17.4 qosc3e - credit_c3_g1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 9 11.9.17.5 qosc3f - credit_c4_g1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 9 11.9.17.6 qosc40 - credit_c5_g1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 9 11.9.17.7 qosc41- credit_c6_g1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 9 11.9.17.8 qosc42- credit_c7_g1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 9 11.9.18 classes wfq credit port g2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 11.9.18.1 qosc43 - credit_c0_g2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 11.9.18.2 qosc44 - credit_c1_g2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 11.9.18.3 qosc45 - credit_c2_g2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 11.9.18.4 qosc46 - credit_c3_g2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 11.9.18.5 qosc47 - credit_c4_g2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 11.9.18.6 qosc48 - credit_c5_g2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 11.9.18.7 qosc49- credit_c6_g2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 11.9.18.8 qosc4a- credit_c7_g2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 11.9.19 classes wfq credit port g3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 11.9.19.1 qosc4b - credit_c0_g3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 11.9.19.2 qosc4 - credit_c1_g3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 11.9.19.3 qosc4d - credit_c2_g3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 11.9.19.4 qosc4e - credit_c3_g3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 11.9.19.5 qosc4f - credit_c4_g3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 11.9.19.6 qosc50 - credit_c5_g3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 11.9.19.7 qosc51- credit_c6_g3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 11.9.19.8 qosc52- credit_c7_g3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 11.9.20 classes wfq credit port g4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 11.9.20.1 qosc53 - credit_c0_g4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 11.9.20.2 qosc54 - credit_c1_g4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 11.9.20.3 qosc55 - credit_c2_g4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 11.9.20.4 qosc56 - credit_c3_g4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 11.9.20.5 qosc57 - credit_c4_g4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 11.9.20.6 qosc58 - credit_c5_g4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 11.9.20.7 qosc59- credit_c6_g4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 11.9.20.8 qosc5a- credit_c7_g4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 11.9.20.9 classes wfq credit port g5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 11.9.20.10 qosc5b - credit_c0_g5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 11.9.20.11 qosc5c - credit_c1_g5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 11.9.20.12 qosc5d - credit_c2_g5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 11.9.20.13 qosc5e - credit_c3_g5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 11.9.20.14 qosc5f - credit_c4_g5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 11.9.20.15 qosc60 - credit_c5_g5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 11.9.20.16 qosc61- credit_c6_g5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 11.9.20.17 qosc62- credit_c7_g5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 11.9.21 classes wfq credit port g6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 11.9.21.1 qosc63 - credit_c0_g6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 11.9.21.2 qosc64 - credit_c1_g6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 11.9.21.3 qosc65 - credit_c2_g6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 11.9.21.4 qosc66 - credit_c3_g6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 11.9.21.5 qosc67 - credit_c4_g6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 11.9.21.6 qosc68 - credit_c5_g6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
mvtx2804 data sheet table of contents 12 zarlink semiconductor inc. 11.9.21.7 qosc69- credit_c6_g6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 11.9.21.8 qosc6a- credit_c7_g6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 11.9.22 classes wfq credit port g7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 11.9.22.1 qosc6b - credit_c0_g7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 11.9.22.2 qosc6c - credit_c1_g7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 11.9.22.3 qosc6d - credit_c2_g7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 11.9.22.4 qosc6e - credit_c3_g7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 11.9.22.5 qosc6f - credit_c4_g7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 11.9.22.6 qosc70 - credit_c5_g7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 11.9.22.7 qosc71- credit_c6_g7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 11.9.22.8 qosc72- credit_c7_g7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 11.9.23 class 6 shaper control port g0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 11.9.23.1 qosc73 - token_rate_g0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 11.9.23.2 qosc74 - token_limit_g0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 11.9.23.3 class 6 shaper control port g1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 11.9.23.4 qosc75 - token_rate_g1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 11.9.23.5 qosc76 - token_limit_g1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 11.9.24 class 6 shaper control port g2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 11.9.24.1 qosc77 - token_rate_g2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 11.9.24.2 qosc78 - token_limit_g2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 11.9.25 class 6 shaper control port g3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 11.9.25.1 qosc79 - token_rate_g3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 11.9.25.2 qosc7a - token_limit_g3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 11.9.26 class 6 shaper control port g4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 11.9.26.1 qosc7b - token_rate_g4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 11.9.26.2 qosc7c - token_limit_g4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 11.9.27 class 6 shaper control port g5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 11.9.27.1 qosc7d - token_rate_g5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 11.9.27.2 qosc7e - token_limit_g5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 11.9.28 class 6 shaper control port g6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 11.9.28.1 accessed by cpu only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 11.9.28.2 qosc7f - token_rate_g6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 11.9.28.3 qosc80 - token_limit_g6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 11.9.29 class 6 shaper control port g7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 11.9.29.1 qosc81 - token_rate_g7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 11.9.29.2 qosc82 - token_limit_g7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 11.9.30 rdrc0 - wred rate control 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 11.9.31 rdrc1 - wred rate control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 11.10 group 6 address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 11.10.1 misc group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 11.10.1.1 mii_op0 - mii register option 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 11.10.1.2 mii_op1 - mii register option 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 11.10.1.3 fen - feature register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 11.10.1.4 miic0 - mii command register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 11.10.1.5 miic1 - mii command register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 11.10.1.6 miic2 - mii command register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 11.10.1.7 miic3 - mii command register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 11.10.1.8 miid0 - mii data register 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 11.10.1.9 miid1 - mii data register 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 11.10.1.10 led mode - led control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 11.10.2 checksum - eeprom checksum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 11.10.3 led user . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
mvtx2804 data sheet table of contents 13 zarlink semiconductor inc. 11.10.3.1 leduser0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 11.10.3.2 leduser1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 11.10.3.3 leduser2/ledsig2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 11.10.3.4 leduser3/ledsig3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 11.10.3.5 leduser4/ledsig4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 11.10.3.6 leduser5/ledsig5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 11.10.3.7 leduser6/ledsig6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 11.10.3.8 leduser7/ledsig1_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 25 11.10.4 miinp0 - mii next page data regist er 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 11.10.5 miinp1 - mii next page data regist er 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 11.11 group f address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 11.11.1 cpu access group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 11.11.1.1 gcr-global control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 11.11.1.2 dcr-device status and signature register . . . . . . . . . . . . . . . . . . . . . . . . . 126 11.11.1.3 dcr01-giga port status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 11.11.1.4 dcr23-giga port status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 11.11.1.5 dcr45-giga port status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 11.11.1.6 dcr67-giga port status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 11.11.1.7 dpst - device port status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 11.11.1.8 dtst - data read back register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 12.0 bga and ball signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 12.1 bga views (top-view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 12.2 ball-signal descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 12.2.1 ball signal description in managed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 12.2.2 ball - signal description in unmanaged mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 12.3 ball signal name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 12.4 characteristics and timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 12.4.1 absolute maxi mum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 12.4.2 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 12.4.3 recommended operating cond itions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159 12.5 ac characteristics and timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 12.5.1 typical reset & bootstrap timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160 12.5.2 typical cpu timing diagram for a cpu write cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 12.5.3 typical cpu timing diagram for a cpu read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 12.5.4 local frame buffer zbt sram memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 12.5.4.1 local zbt sram memory interface a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 12.5.4.2 local zbt sram memory interface b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 12.5.5 local switch database sbram memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 12.5.5.1 local sbram memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5 12.5.6 media independent interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 12.5.7 gigabit media independent interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 12.5.8 pcs interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 12.5.9 led interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 12.5.10 mdio input setup and hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 12.5.11 i 2 c input setup timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 12.5.12 serial interface setup timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
mvtx2804 data sheet list of figures 14 zarlink semiconductor inc. figure 1 - MVTX2804Ag functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2 - overview of the mtvtx2804ag cp u interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 3 - data transfer format for i 2 c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 4 - mvtx2804 sram interface bloc k diagram (dmas for gigaport ports) . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 5 - buffer partition scheme used in the mvtx2804. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 6 - mvtx2804 features enabling ietf diffserv standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 7 - timing diagram for serial mode in led interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 8 - typical reset & bootstrap timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 figure 9 - typical cpu timing diagram for a cpu write cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 figure 10 - typical cpu timing diagram for a cpu read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 figure 11 - local memory interface ? input setup and hold timi ng . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 figure 12 - local memory interface - output valid delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 figure 13 - local memory interface ? input setup and hold timi ng . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 figure 14 - local memory interface - output valid delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 figure 15 - local memory interface ? input setup and hold timi ng . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 figure 16 - local memory interface - output valid delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 figure 17 - ac characteristics ? media in dependent interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 figure 18 - ac characteristics ? media in dependent interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 figure 19 - ac characteristics - gmii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 figure 20 - ac characteristics ? gigabit media independent interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 figure 21 - ac characteristics ? pcs interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 figure 22 - ac characteristics ? pcs interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 figure 23 - ac characteristics ? led interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 figure 24 - mdio input setup and hold timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 figure 25 - mdio output delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 figure 26 - i 2 c input setup timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 figure 27 - i 2 c output delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 figure 28 - serial interface setup timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 figure 29 - serial interface output delay timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
mvtx2804 data sheet list of tables 15 zarlink semiconductor inc. table 1 - two-dimensional world traffic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 2 - four qos configurations per port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 3 - wred dropping scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 4 - mapping between mvtx2804 and ietf diffserv classes for gigabit ports . . . . . . . . . . . . . . . . . . . . . . 34 table 5 - reset & bootstrap timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 table 6 - cpu write cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 table 7 - cpu read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 table 8 - ac characteristics ? local frame buffer zbt-sram memo ry interface a . . . . . . . . . . . . . . . . . . . . . . 163 table 9 - ac characteristics ? local frame buffer zbt-sram memo ry interface b . . . . . . . . . . . . . . . . . . . . . . 164 table 10 - ac characteristics ? local switch database sbram me mory interface . . . . . . . . . . . . . . . . . . . . . . 165 table 11 - ac characteristics ? media independent interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 table 12 - ac characteristics ? gigabit media independent interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 table 13 - ac characteristics ? pcs interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 table 14 - ac characteristics ? led interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 table 15 - mdio timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 table 16 - i 2 c timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 table 17 - serial interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
mvtx2804 data sheet 16 zarlink semiconductor inc. 1.0 block functionality 1.1 frame data buffer (fdb) interfaces the fdb interface supports pipelined zbt-sram memory at 133 mhz. to ensure a non-blocking switch, two memory domains are required. each domain has a 64-bit wide memory bus. at 133 mhz, the aggregate memory bandwidth is 17 gbps, which is enough to support 8 gi gabit ports at full wire speed switching. a patent pending scheme is used to access the fdb memory. each slot has one tick to read or write 8 bytes. 1.2 switch database (sdb) interface a pipelined synchronous burst sram (sbram) memory is used to store the switch database information including mac table, vlan table and ip multicast t able. search engine accesses the switch database via sdb interface. the sdb memory has 32-bit wide bus at 133mhz. 1.3 gmii/pcs mac module (gmac) the gmii/pcs media access control (mac) module prov ides the necessary buffers and control interface between the frame engine (fe) and the external physica l device (phy). the mvtx2804 has two interfaces, gmii or pcs. the mac of the mvtx2804 meets the ieee 802 .3z specification and supports the mii interface. it is able to operate in 10m/100m/1g in full duplex mode with a flow control mechanism. it has the options to insert source address/crc/vlan id to each frame. the gmii/pcs module also supports hot plug detection. 1.4 cpu interface module one extra port is dedicated to the cpu via the cpu inte rface module. the cpu interf ace utilizes a 16/8-bit bus in managed mode. it also supports a serial and an i 2 c interface, which provides an easy way to configure the system if unmanaged. 1.5 management module the cpu can send a control frame to access or configure the internal network management database. the management module decodes the control frame and ex ecutes the functions requested by the cpu. 1.6 frame engine the main function of the frame engine is to forward a frame to its proper destination port or ports. when a frame arrives, the frame engine parses the frame header (64 by tes) and formulates a switching request, which is sent to the search engine to resolve the destination port. the a rriving frame is moved to the fdb. after receiving a switch response from the search engine, the fram e engine performs transmission scheduling based on the frame's priority. the frame engine forwards the frame to the mac module when the frame is ready to be sent. 1.7 search engine the search engine resolves the frame's destination port or ports according to the destination mac address (l2) or ip multicast address (ip multicast packet) by searchi ng the database. it also perf orms mac learning, priority assignment, and trunking functions. 1.8 led interface the led interface can be operated in a serial mode or a parallel mode. in the serial mode, the led interface uses 3 pins for carrying 8 port status signals. in the para llel mode, the interface can drive leds by 8 status pins. the led port is shared with bootstrap pins. in order to avoid mis-reading a buffer must be used to isolate the led circuitry from the bootstrap pins during bootstrap cycle (the bootstraps are sampled at the rising edge of the #reset).
mvtx2804 data sheet 17 zarlink semiconductor inc. 1.9 internal memory several internal tables are required and are described as follows: ? frame control block (fcb) - each fcb entry contains the control information of the associated frame stored in the fdb, e.g. frame size, read/writ e pointer, transmission priority, etc. ? network management (nm) database - the nm database co ntains the information in the statistics counters and mib. ? mct link table - the mct link table stores the linked li st of mct entries that have collisions in the external mac table. ? vlan port aging table - this table provides the agi ng status of vlan port association status. search engine maintains this table and informs the cpu when the entry is ready to age out. 2.0 system configuration 2.1 management and configuration two modes are supported in the mvtx2804: managed and unmanaged. in managed mode, the mvtx2804 uses an 8- or 16-bit cpu interface very similar to the industry standard architecture (isa) specification. in unmanaged mode, the mvtx2804 has no cpu but can be configured by eeprom using an i 2 c interface at bootup, or via a synchronous serial interface otherwise. 2.2 managed mode in managed mode, the mvtx2804 uses an 8- or 16-bit cpu interface very similar to the isa bus. the mvtx2804 cpu interface provides for easy and effective management of the switching system. the figure below provides an overview of the cpu interface.
mvtx2804 data sheet 18 zarlink semiconductor inc. figure 2 - overview of the mtvtx2804ag cpu interface 2.3 register configuration, frame transmission, and frame reception the mvtx2804 has many programmable parameters, coveri ng such functions as qos weights, vlan control. in managed mode, the cpu interface provides an easy way of configuring these parameters. the parameters are contained in 8-bit configuration registers. the mvtx2804 allows indirect access to these registers, as follows: ? ? two ?index? registers (addresses 000 and 001) need to be written, to indicate the desired 16-bit register address. ? ? to indirectly configure the register addressed by the two index registers, a ?configure data? register (address 010) must be written with the desired 8-bit data. ? ? similarly, to read the value in the register addressed by the two index registers, the ?configure data? register can now simply be read. in summary, access to the many internal registers is carrie d out simply by directly accessing only three registers ? two registers to indicate the address of the desired parame ter, and one register to read or write a value. of course, cpu frame receiver fifo i/o mux index reg 1 (addr = 001) index reg 0 (addr = 000) response reg (addr = 111) config (addr = 010) (addr = 011) command/ (addr = 100) interrupt reg (addr = 101) control frame (addr = 110) data reg data reg status reg (ro) cpu frame cpu frame transmit fifo internal registers synchronous serial interface i/o mux 16-bit address interrupt 8/16-bit data bus frame recent fifo frame transmit fifo1 frame transmit fifo2 8/16-bit 8-bit 3-bit addr 8/16-bit data bus process mux search engine q0 q1 rd_cyc, wr_cyc to rate control ram statistic counter ram fcb ram mct ram external sram vlan index cpu interface data bus data bus data reg
mvtx2804 data sheet 19 zarlink semiconductor inc. because there is only one bus master, there can nev er be any conflict between reading and writing the configuration registers. 2.3.1 ethernet frames the cpu interface is also responsible for receiving and transmitting standard ethernet frames to and from the cpu. to transmit a frame from the cpu ? the cpu writes a ?data frame? register (address 011) with the data it wants to transmit. after writing all the data, it then writes the frame size, destination port number, and frame status. ? the mvtx2804 forwards the ethernet frame to the desire d destination port, no longer distinguishing the fact that the frame originated from the cpu. to receive a frame into the cpu ? the cpu receives an interrupt when an ethe rnet frame is available to be received. ? frame information arrives first in the data frame register. this includes source port number, frame size, and vlan tag. ? the actual data follows the frame information. the cp u uses the frame size information to read the frame out. in summary, receiving and transmitting frames to and from the cpu is a simple process that uses one direct access register only. 2.3.2 control frames in addition to standard ethernet frames described in th e preceding section, the cpu is also called upon to handle special ?control frames,? generated by the mvtx2 804 and sent to the cpu. these proprietary frames are related to such tasks as statistics collection, mac address learning, aging, etc. all control frames are 64 bytes long. transmitting and receiving these frames is similar to transmi tting and receiving ethernet frames, except that the register accessed is the ?control frame data? register (address 110). specifically, there are eight types of control frames generated by the cpu and sent to the mvtx2804: ? memory read request ? memory write request ? learn mac address ? delete mac address ? search mac address ? learn ip multicast address ? delete ip multicast address ? search ip multicast address note: memory read and write requests by the cpu may incl ude vlan table, spanning tree, statistic counters, and similar updates. in addition, there are nine types of control fram es generated by the mvtx2804 and sent to the cpu: ? interrupt cpu when statistics counter rolls over ? response to memory read request from cpu ? learn mac address ? delete mac address ? delete ip multicast address ? new vlan port ? age out vlan port ? response to search mac address request from cpu ? response to search ip multicast address request from cpu
mvtx2804 data sheet 20 zarlink semiconductor inc. note: deleting ip multicast address requests by the mvtx28 04 occur when the cpu issues a learn ip multicast address command but the search engine discovers no ram space for storage. the format of the control frame is described in the processor interface application note. 2.4 unmanaged mode in unmanaged mode, the mvtx2804 can be configured by eeprom (24c02 or compatible) via an i 2 c interface at boot time, or via a synchronous serial interface during operation. when the bootstrap td[8] is set to ?0? meaning eeprom installed, th e mvtx2804, acting as a master starts t he data transfer from the memory to the switch. 2.5 i 2 c interface the i 2 c interface uses two bus lines, a serial data line (sda ) and a serial clock line (scl). the scl line carries the control signals that facilitate the transfer of informa tion from eeprom to the swit ch. data transfer is 8-bit serial and bi-directional, at 50 kbps. data transfer is performed between master and slave ic using a request / acknowledgment style of protocol. the master ic generat es the timing signals and terminates data transfer. the figure below shows the data transfer format. figure 3 - data transfer format for i 2 c interface 2.5.1 start condition generated by the master, the mvtx2804. the bus is considered to be busy after the start condition is generated. the start condition occurs if while the scl line is high, there is a high-to-low transition of the sda line. other than in the start condition (and stop condition), t he data on the sda line must be stable during the high period of scl. the high or low state of sda c an only change when scl is low. in addition, when the i 2 c bus is free, both lines are high. 2.5.2 address the first byte after the start condition determines which slave the master will select. the slave in our case is the eeprom. the first seven bits of the first data byte make up the slave address. 2.5.3 data direction the eighth bit in the first byte after the start conditi on determines the direction (r/w) of the message. a master transmitter sets this bit to w; a master receiver sets this bit to r. 2.5.4 acknowledgment like all clock pulses, the master generates the ack nowledgment-related clock pulse. however, the transmitter releases the sda line (high) during the acknowledgment clock pulse. furthermore, the receiver must pull down the sda line during acknowledge pulse so that it remain s stable low during the high period of this clock pulse. an acknowledgment pulse follows every byte transfer. if a slave receiver does not acknowledge after any by te, then the master generates a stop condition and aborts the transfer. start slave address r/w ack data 1 (8 bits) ack data 2 ack data m ack stop
mvtx2804 data sheet 21 zarlink semiconductor inc. if a master receiver does not acknowledge after any byte , then the slave transmitter must release the sda line to let the master generate the stop condition. 2.5.5 data after the first byte containing the address, all bytes that follow are data bytes. each byte must be followed by an acknowledge bit. data is transferred msb-first. 2.5.6 stop condition generated by the master. the bus is considered to be free after the stop condition is generated. the stop condition occurs if while the scl line is high, there is a low-to-high transition of the sda line. the i 2 c interface serves the function of configuring t he mvtx2804 at boot time. the master is the mvtx2804, and the slave is the eeprom memory. 2.6 synchronous serial interface the synchronous serial interface serves the function of conf iguring the mvtx2804 not at boot time but via a pc. the pc serves as master and the mvtx2804 serves as slave. the protocol for the synchronous serial interface is nearly identical to the i 2 c protocol. the main difference is that there is no acknowledgment bit after each byte of data transferred. the unmanaged mvtx2804 uses a synchronous serial interfac e to program the internal registers. to reduce the number of signals required, the register address, command and data are shifted in serially through the ps_di pin. ps_strobe pi n is used as the shift clock. ps_do pin is used as data return path. each command consists of four parts. ? start pulse ? register address ? read or write command ? data to be written or read back any command can be aborted in the middle by sending an abort pulse to the mvtx2804. a start command is detected when ps_di is sampl ed high at ps_strobe - leading edge, and ps_di is sampled low when ps_strobe- falls. an abort command is detected when ps_di is samp led low at ps_strobe - leading edge, and ps_di is sampled high when ps_strobe - falls.
mvtx2804 data sheet 22 zarlink semiconductor inc. 2.6.1 write command 2.6.2 read command all registers in the mvtx2804 can be modified through this synchronous serial interface. 3.0 data forwarding protocol 3.1 unicast data frame forwarding when a frame arrives, it is assigned a handle in memory by the frame control buffer manager (fcb manager). an fcb handle will always be available, because of advance buffer reservations. the memory (zbt-sram) interface is two 64-bit buses , connected to two zbt-sram domains, a and b. the receive dma (rxdma) is responsible for multiplexing the data and the address. on a port's ?turn,? the rxdma will move 8 bytes (or up to the end-of-frame) from t he port's associated rxfifo into memory (frame data buffer, or fdb). once an entire frame has been moved to the fdb, and a good end-of-frame (eof) has been received, the rx interface makes a switch request. the rxdma arbitrates among multiple switch requests. the switch request consists of the first 64 bytes of a frame, containing among other things, the source and destination mac addresses of the frame. the search engi ne places a switch response in the switch response queue of the frame engine when done. among other informat ion, the search engine will have resolved the destination port of the frame and will have determined that the frame is unicast. after processing the switch response, the transmission queue manager (txq manager) of the frame engine is responsible for notifying the destination port that it has a frame to forward to it. but first, the txq manager has to decide whether or not to drop the frame, based on global fdb reservations and usage, as well as txq ps-strobe- ps_di a0 a2 ... a9 a10 a11 a1 w d0 d1 d2 d3 d4 d5 d6 d7 start address command data 2 extra clocks after last transfer ps_strobe- ps_di ps_do a0 a1 a2 ... a9 a10 a11 r d0 d1 d2 d3 d4 d5 d6 d7 start address command data
mvtx2804 data sheet 23 zarlink semiconductor inc. occupancy at the destination. if the frame is not dropped, then the txq manager links the frame's fcb to the correct per-port-per-class txq. unicast txq's are linked lists of transmission jobs, represented by their associated frames' fcbs. there is one linked list for eac h transmission class for each port. there are 8 classes for each of the 8 gigabit ports - a total of 32 unicast queues. the txq manager is responsible for scheduling trans mission among the queues representing different classes for a port. when the port control module determines that there is room in the mac transmission fifo (txfifo) for another frame, it requests the handle of a new frame from the txq manager. the txq manager chooses among the head-of-line (hol) frames from the per-class queues for that port, using a zarlink semiconductor scheduling algorithm. as at the transmit end, each of the 8 ports has time slots devoted solely to reading data from memory at the address calculated by port control. the transmission dm a (txdma) is responsible for multiplexing the data and the address. on a port's turn, the txdma will move 8 bytes (or up to the eof) from memory into the port's associated txfifo. after reading the eof, the port cont rol requests a fcb release for that frame. the txdma arbitrates among multiple buffer release requests. the frame is transmitted from the txfifo to the line. 3.2 multicast data frame forwarding after receiving the switch response, the txq manager has to make the dropping decision. a global decision to drop can be made, based on global fdb utilization and reservations. if so, then the fcb is released and the frame is dropped. in addition, a selective decision to drop can be made, based on the txq occupancy at some subset of the multicast packet's destinations. if so, then the frame is dropped at some destinations but not others, and the fcb is not released. if the frame is not dropped at a particular destination port, then the txq manager formats an entry in the multicast queue for that port and class. multicast queues are physical queues (unlike the linked lists for unicast frames). there are 4 multicast queues for each of the 8 gigabit ports. there is one multicast queue for every two unicast classes. during scheduling, the txq manager treats the unicast queue and the multicast queue of the same class as one logical queue. the port control requests a fcb release only after the eof for the multicast frame has been read by all ports to which the frame is destined. 3.3 frame forwarding to and from cpu frame forwarding from the cpu port to a regular trans mission port is nearly the same as forwarding between transmission ports. the only difference is that the physica l destination port must be indicated in addition to the destination mac address. if an invalid port is indicated the frame is forwarded accordingly to the destination mac address. frame forwarding to the cpu port is nearly the same as forwarding to a regular transmission port. the only difference is in frame scheduling. instead of usi ng the patent-pending scheduling algorithms, scheduling for the cpu port is simply based on strict priority. that is, a frame in a high priority queue will always be transmitted before a frame in a lower priority queue. there ar e four output queues to the cpu and one receive queue.
mvtx2804 data sheet 24 zarlink semiconductor inc. 4.0 memory interface 4.1 overview the figure below illustrates the first part of the zbt-sram interface for the mvtx2804. as shown, two zbt-sram banks a and b are used, with a 64-bit bus c onnected to each. each dma can read and write from both bank a and bank b. during each ti ck, two memory operations will take place in parallel - one for bank a, and one for bank b. because the clock frequency is 133 mhz, the total memory bandwidth is 128 bits 133 mhz = 17 gbps, for frame data buffer (fdb) access. in addition, the figure shows that the 8 gigabit ports are actually grouped into sets of 4. if txdma 0 is using bank b during a given memory slot, then txdma's 1-3 will never be using ba nk a during this same slot. as a result, txdma's 0-3 can share the same bank selector. not shown in the figure are the cpu port rxdma's and txdma's, each separately connected to its own bank selector. figure 4 - mvtx2804 sram interface bl ock diagram (dmas for gigaport ports) 4.2 detailed memory information because the bus for each bank is 64 bits wide, frames are broken into 8-byte granules, written to and read from memory. the first 8-byte granule gets written to bank a, the second 8-byte granule gets written to bank b, and so on in alternating fashion. when reading frames fr om memory, the same procedure is followed, first from a, then from b, and so on. the reading and writing from alternating memory banks can be performed with minimal waste of memory bandwidth. what's the worst case? for any speed port, in the worst case, a 1-byte-long eof granule gets written to bank a. this means that a 7-byte segment of bank a bandwidth is idle, and furthermore, the next 8-byte segment of bank b bandwidth is idle, because the first 8 bytes of the next frame will be written to bank a, not b. this scenario results in a maximum 15 bytes of waste per frame, which is always acceptable because the interframe gap is 20 bytes. the cpu management port gets treated like any other port, reading and writing to alternating memory banks starting with bank a. search engine data is written to both banks in parallel. in this way, a search engine read operation could be performed by either bank at any time without a problem. zbt-sram bank a zbt-sram bank b 0-1 txdma 2-3 txdma 4-5 txdma 6-7 txdma 0-1 rxdma 2-3 rxdma 4-5 rxdma 6-7 rxdma
mvtx2804 data sheet 25 zarlink semiconductor inc. 5.0 search engine 5.1 search engine overview the mvtx2804 search engine is optimized for high thr oughput searching, with enhanced features to support: ? up to 64k mac addresses ? up to 4k vlan ? up to 64k ip multicast groups ? 4 groups of port trunking ? traffic classification into 8 transmiss ion priorities, and 2 drop precedence levels ? packet filtering ?security ?ip multicast ? per port, per vlan spanning tree 5.2 basic flow shortly after a frame enters the mvtx2804 and is written to the frame data buffer (fdb), the frame engine generates a switch request, which is sent to the sear ch engine. the switch request consists of the first 64 bytes of the frame, which contain all the necessary info rmation for the search engine to perform its task. when the search engine is done, it writes to the switch response queue, and the frame engine uses the information provided in that queue for scheduling and forwarding. in performing its task, the search engine extracts and compresses the useful information from the 64-byte switch request. among the information extracted ar e the source and destination mac addresses, the transmission and discard priorities, whether the frame is unicast or multicast, and vlan id. requests are sent to the external sram switch database to locate the associated entries in the external mct table. when all the information has been collected from extern al sram, the search engine has to compare the mac address on the current entry with the mac address for which it is searching. if it is not a match, the process is repeated on the internal mct table. all mct entries other than the first of each linked list are maintained internal to the chip. if the desired mac address is still not found, then the result is either learning (source mac address unknown) or flooding (destination mac address unknown). in addition, vlan information is used to select the correct set of destination ports for the frame (for multicast), or to verify that the frame's destination port is associated with the vlan (for unicast). if the destination mac address belongs to a port trunk, then the trunk number is retrieved instead of the port number. but on which port of the trunk will the frame be transmitted? this is easily computed using a hash of the source and destination mac addresses. when all the information is compiled, the switch res ponse is generated, as stated earlier. the search engine also interacts with the cpu with regard to learning and aging. 5.3 search, learning, and aging 5.3.1 mac search the search block performs source mac address and des tination mac address (or destination ip address for ip multicast) searching. as we indicated earlier, if a matc h is not found, then the next ent ry in the linked list must be examined, and so on until a match is f ound or the end of the list is reached. in tag based vlan mode, if the frame is unicast, and the destination port is not a member of the correct vlan, then the frame is dropped; otherwise, the frame is forwarded. if the frame is multicast, this same table is used to
mvtx2804 data sheet 26 zarlink semiconductor inc. indicate all the ports to which the frame will be forw arded. moreover, if port trunking is enabled, this block selects the destination port (among those in the trunk group). in port based vlan mode, a bitmap is used to determine whether the frame should be forwarded to the outgoing port. the main difference in this mode is that the bitmap is not dynamic. ports cannot enter and exit groups because of real-time learning made by a cpu. the mac search block is also responsible for updating the source mac address timestamp and the vlan port association timestamp, used for aging. 5.3.2 learning the learning module learns new mac addresses a nd performs port change operations on the mct database. the goal of learning is to update this database as the networking environment changes over time. when cpu reporting is enabled, learning and port change will be performed when the cpu request queue has room, and a memory slot is available, and a ?learn mac address? message is sent to the cpu. when cpu reporting is disabled, learning and port change will be perfor med based on memory slot availability only. in tag based vlan mode, if the source port is not a member of a classified vlan, a ?new vlan port? message is sent to the cpu. the cpu can decide whether or not the source port can be added to the vlan. 5.3.3 aging aging time is controlled by register 400h and 401h. the aging module scans and ages mct entries based on a programmable ?age out? time interval. as we indicated earlier, the search module updates the source mac address and vlan port association timestamps for each frame it processes. when an entry is ready to be aged, the entry is removed from the table, and a ?delete mac address? message is sent to inform the cpu. supported entry types are dynamic, static, source filter, destination filter, ip multicast, source and destination filter, and secure mac address. only dynamic entries can be aged; whether an entry is static or dynamic is maintained in the ?status? field of the mct data structure. 5.3.4 data structure the mct data structure is used for searching for mac addresses. the structure is maintained by hardware in the search engine. the cpu can make requests to add to, delete from, or search the mct database. the database is essentially a hash table, with collisions reso lved by chaining. the database is partially external, and partially internal, as described earlier: the first mct entry of each linked list is always located in the external sram, and the subsequent mcts are located internally. 5.3.5 vlan port association table 31 30 29 27 26 0 valid route reserved port 8 to 0 is vlan status port 8 port 7 port 6 port 5 port 4 port 3 port 2 port 1 port 0 vlan status vlan status vlan status vlan status vlan status vlan status vlan status vlan status vlan status
mvtx2804 data sheet 27 zarlink semiconductor inc. vlan status [2:0] ? 000:not a valid entry ? 001:blocking status, no rx and tx ? 010:not a vlan member, spanning tree learn status ? 011:vlan member, spanning tree learn status ? 100:not a vlan member, spanning tree forward status ? 101:vlan member and is subject to aging, spanning tree forward status (don't use) ? 110:vlan member and is subject to aging, spanning tree forward status ? 111:vlan member and is not subject to aging, spanning tree forward status cpu can create static vlan port by writing the st atic status to the vlan- port status entry. dynamic vlan and port association can be created by wr iting ?110? to the vlan status. hardware will age and refresh the entry based on the vlan - port activi ty. when the vlan - port is ready to be aged out, a message is sent to cpu and cpu can remove the vlan - port association by writing ?000? to the vlan status. as a result, the vlan and port are no long associated and the vlan domain is shrunk. 6.0 frame engine 6.1 data forwarding summary ? enters the device at the rxmac, the rxdma will move the data from the mac rxfifo to the fdb. data is moved in 8-byte granules in conjunction with the scheme for the sram interface. ? a switch request is sent to the search engine. the search engine processes the switch request. ? a switch response is sent back to the frame engine and indicates whether the frame is unicast or multicast, and its destination port or ports. a vlan table lookup is performed as well. ? a transmission scheduling request is sent in the form of a signal notifying the txq manager. upon receiving a transmission scheduling request, the device will format an entry in the appropriate transmission scheduling queue (txsch q) or queues . there is 8 transmission queues per gigabit port, one for each priority. creation of a queue entry either involves linking a new job to the appropriate linked list if unicast, or adding an entry to a physical queue if multicast. ? when the port is ready to accept the next frame, the txq manager will get the head-of-line (hol) entry of one of the txsch qs, according to the transmission scheduling algorithm (so as to ensure per-class quality of service). the unicast linked list and the multicas t queue for the same port-class pair are treated as one logical queue. ? the txdma will pull frame data from the memory and forward it granule-by-granule to the mac txfifo of the destination port. 6.2 frame engine details this section briefly describes the functions of each of the modules of the mvtx2804 frame engine. 6.2.1 fcb manager the fcb manager allocates fcb handles to incoming frames, and releases fcb handles upon frame departure. the fcb manager is also responsible for enfor cing buffer reservations and limits. the default values can be determined by referring to chapter 8. in addition , the fcb manager is responsible for buffer aging, and for linking unicast forwarding jobs to their correct txsch q. the buffer aging can be enabled or disabled by the bootstrap pin and the aging time is defined in register fcbat.
mvtx2804 data sheet 28 zarlink semiconductor inc. 6.2.2 rx interface the rx interface is mainly responsible for communicati ng with the rxmac. it keeps track of the start and end of frame and frame status (good or bad). upon receiving an end of frame that is good, the rx interface makes a switch request. 6.2.3 rxdma the rxdma arbitrates among switch requests from each rx interface. it also buffers the first 64 bytes of each frame for use by the search engine when the switch request has been made. 6.2.4 txq manager first, the txq manager checks the per-class queue status and global reserved resource situation, and using this information, makes the frame dr opping decision after receiving a switch response. if the decision is not to drop, the txq manager requests that the fcb manager link the unicast frame's fcb to the correct per-port-per-class txq. if multicast, the txq manager writes to the multicast queue for that port and class. the txq manager can also trigger source port flow control for t he incoming frame's source if that port is flow control enabled. second, the txq manager handles transmission scheduling; it schedules transmission among the queues representing different classes for a port. once a frame has been scheduled, the txq manager reads the fcb information and writes to the correct port control module. 6.3 port control the port control module calculates the sram read addr ess for the frame currently being transmitted. it also writes start of frame information and an end of frame flag to the mac txfifo. when transmission is done, the port control module requests that the buffer be released. 6.4 txdma the txdma multiplexes data and address from port control, and arbitrates among buffer release requests from the port control modules. 7.0 quality of se rvice and flow control 7.1 model quality of service (qos) is an all-encompassing term fo r which different people have different interpretations. in this chapter, by quality of service assurances, we mean the allocation of chip resources so as to meet the latency and bandwidth requirements associated with each traffic class. we do not presuppose anything about the offered traffic pattern. if the traffic load is light, then ensuring quality of service is straightforward. but if the traffic load is heavy, the mvtx2804 must intelligently alloca te resources so as to assure quality of service for high priority data. we assume that the network manager knows his applications , such as voice, file transfer, or web browsing, and their relative importance. the manager can then subdivi de the applications into classes and set up a service contract with each. the contract may consist of bandwidt h or latency assurances per class. sometimes it may even reflect an estimate of the traffic mix offere d to the switch, though this is not required. the table below shows examples of qos applications wi th eight transmission priorities, including best effort traffic for which we provide no bandwidth or latency assurances.
mvtx2804 data sheet 29 zarlink semiconductor inc. in our model, it is possible that a class of traffic may attempt to monopolize system resources by sending data at a rate in excess of the contractually assured bandwidth for that class. a well-behaved class offers traffic at a rate no greater than the agreed-upon rate. by contrast, a misbehaving class offers traffic that exceeds the agreed-upon rate. a misbehaving class is formed from an aggregation of misbehaving microflows. to achieve high link utilization, a mi sbehaving class is allowed to use any idle bandwidth. however, the quality of service (qos) received by well-behaved classes must never suffer. as table 1 illustrates, each traffic class may have it s own distinct properties and applications. as shown, classes may receive bandwidth assurances or latency bounds. in the example, p7, the highest transmission class, requires that all frames be transmitted within 0.2 ms , and receives 30% of the 1 gbps of bandwidth at that port. best-effort (p1-p0) traffic forms a lower tier of se rvice that only receives ba ndwidth when none of the other classes have any traffic to offer. in addition, each transmission class has two subclasse s, high-drop and low-drop. well-behaved users should not lose packets. but poorly behaved users - users who send data at too high a rate - will encounter frame loss, and the first to be discarded will be high-drop. of course, if this is insufficient to resolve the congestion, eventually some low-drop frames are dropped as well. table 1 shows that different types of applications may be placed in different boxes in the traffic table. for example, web search may fit into the category of high-loss , high-latency-tolerant traffic, whereas voip fits into the category of low-loss, low-latency traffic. class example assured bandwidth (user defined) low drop subclass (if class is oversubscribed, these packets are the last to be dropped.) high drop subclass (if class is oversubscribed, these packets are the first to be dropped.) highest transmission priorities, p7 latency < 200 s 300 mbps sample application: control information highest transmission priorities, p6 latency < 200 s 200 mbps sample applications: phone calls; circuit emulation sample application: training video; other multimedia middle transmission priorities, p5 latency < 400 s 125 mbps sample application: interactive activities sample application: non-critical interactive activities middle transmission priorities, p4 latency < 800 s 250 mbps sample application: web business sample application: non-critical interactive activities low transmission priorities, p3 latency < 1600 s 80 mbps sample application: file backups low transmission priorities, p2 latency < 3200 s 45 mbps sample application: email sample application: web research best effort, p1-p0 - sample application: casual web browsing total 1 gbps table 1 - two-dimensional world traffic
mvtx2804 data sheet 30 zarlink semiconductor inc. 7.2 four qos configurations there are four basic pieces to qos scheduling in the mvtx2804: strict priority ( sp), delay bound, weighted fair queuing (wfq), and best effort (be). using these four pi eces, there are four different modes of operation, as shown in table 2. the default configuration is six delay-bounded queues a nd two best-effort queues. the delay bounds per class are 0.16 ms for p7 and p6, 0.32 ms for p5, 0.64 ms for p4, 1.28 ms for p3, and 2.56 ms for p2 . best effort traffic is only served when there is no delay-bounded traffic to be served. p1 has strict priority over p0. we have a second configuration in which there are two strict priority queues, four delay bounded queues, and two best effort queues. the delay bounds per class are 0.32 ms for p5, 0.64 ms for p4, 1.28 ms for p3, and 2.56 ms for p2. if the user is to choose this configur ation, it is important that p7-p6 (sp) traffic be either policed or implicitly bounded (e.g. if the incoming sp traffi c is very light and predictably patterned). strict priority traffic, if not admission-controlled at a prior stage to the mvtx2804, can have an adverse effect on all other classes' performance. p7 and p6 are both sp classes, and p7 has strict priority over p6. the third configuration contains two strict priority queues and six queues receiving a bandwidth partition via wfq. as in the second configuration, strict pr iority traffic needs to be carefully controlled. in the fourth configuration, all queues are served using a wfq service discipline. 7.3 delay bound in the absence of a sophisticated qos server and signal ling protocol, the mvtx2804 may not be assured of the mix of incoming traffic ahead of time. to cope with this uncertainty, our delay assurance algorithm dynamically adjusts its scheduling and dropping criteria, guided by the queue occupancies and the due dates of their head-of-line (hol) frames. as a result, we assure lat ency bounds for all admitted frames with high confidence, even in the presence of system-wide congestion. our algorithm identifies misbehav ing classes and intelligently discards frames at no detriment to well-behaved cla sses. our algorithm also differentiates between high-drop and low-drop traffic with a weighted random early drop (wred) approach. random early dropping prevents congestion by randomly dropping a percentage of high-drop frames even before the chip's buffers are completely full, while still largely sparing low-drop frames. this allows high-drop frames to be discarded early, as a sacrifice for future low-drop frames. finally, the delay bound algorithm also achieves bandwidth partitioning among classes. 7.4 strict priority and best effort when strict priority is part of the scheduling algorithm, if a queue has even one frame to transmit, it goes first. two of our four qos configurations include strict priority queues. the goal is for strict priority classes to be used for ietf expedited forwarding (ef), where performance guar antees are required. as we have indicated, it is important that strict priority traffic be either polic ed or implicitly bounded, so as to keep from harming other traffic classes. when best effort is part of the scheduling algorithm , a queue only receives bandwidth when none of the other classes have any traffic to offer. two of our four qos configurations include best effort queues. the goal is for p7 p6 p5 p4 p3 p2 p1 p0 op1 (default) delay bound be op2 sp delay bound be op3 sp wfq op4 wfq table 2 - four qos configurations per port
mvtx2804 data sheet 31 zarlink semiconductor inc. best effort classes to be used for non-essential traffic, because we provide no assurances about best effort performance. however, in a typical network setting, mu ch best effort traffic will indeed be transmitted, and with an adequate degree of expediency. because we do not provide any delay assurances for best effort traffic, we do not enforce latency by dropping best effort traffic. furthermore, because we assume that strict priority traffic is carefully controlled before entering the mvtx2804, we do not enforce a fair bandwidth partition by dropping strict priority traffic. to summarize, dropping to enforce quality of service (i.e. bandwidth or delay) does not apply to strict priority or best effort queues. we only drop frames from best effort and strict priority queues when global buffer resources become scarce. 7.5 weighted fair queuing in some environments - for example, in an environment in which delay assurances are not required, but precise bandwidth partitioning on small time scales is essential - wfq may be preferable to a delay-bounded scheduling discipline. the mvtx2804 provides the user with a wfq option with the understanding that delay assurances cannot be provided if the incoming traffic patt ern is uncontrolled. the user sets eight wfq ?weights? such that all weights are whole numbers and sum to 64. this provides per-class bandwidth partitioning with error within 2%. in wfq mode, though we do not assure frame latency, the mvtx2804 still retains a set of dropping rules that helps to prevent congestion and trigger higher level protocol end-to-end flow control. as before, when strict priority is combined with wfq, we do not have special dropping rules for the strict priority queues, because the input traffic pattern is assumed to be carefully controlled at a prior stage. however, we do indeed drop frames from sp queues for global buffer management purposes. in addition, queues p1 and p0 are treated as best effort from a dropping perspective, though they still are assured a percentage of bandwidth from a wfq scheduling perspective. what this means is that these particular queues are only affected by dropping when the global buffer count becomes low. 7.6 shaper although traffic shaping is not a primary function of the mvtx2804, the chip does implement a shaper for expedited forwarding (ef). our goal in shaping is to control the peak and av erage rate of traffic exiting the mvtx2804. shaping is limited to class p6 (the second highe st priority). this means that class p6 will be the class used for ef traffic. (by contrast, we assume class p7 will be used for control packets only.) if shaping is enabled for p6, then p6 traffic must be scheduled using strict priority. with reference to table 2, only the middle two qos configurations may be used. peak rate is set using a programmable whole number, no greater than 64 (register qos-credit_c6_gn). for example, if the setting is 32, then the peak rate for shaped traffic is 32/64 1000 mbps = 500 mbps. average rate is also a programmable whole number, no greater than 64, and no greater than the peak rate. for example, if the setting is 16, then the average rate for shaped traffi c is 16/64 1000 mbps = 250 mbps. as a consequence of the above settings in our example, shaped traffic will ex it the mvtx2804 at a rate always less than 500 mbps, and averaging no greater than 250 mbps. also, when shaping is enabled, it is pos sible for a p6 queue to explode in length if fed by a greedy source. the reason is that a shaper is by definition not work-cons erving; that is, it may hold back from sending a packet even if the line is idle. though we do have global resource management, we do nothing to prevent this situation locally. we assume sp traffic is policed at a prior stage to the mvtx2804.
mvtx2804 data sheet 32 zarlink semiconductor inc. 7.7 wred drop threshold management support to avoid congestion, the weighted random early detection (wred) logic drops packets according to specified parameters. the following table summar izes the behaviour of the wred logic. in the table, |px| is the byte count in queue px. th e wred logic has three drop levels, depending on the value of n, which is based on the number of bytes in the priority queues. if delay bound scheduling is used, n equals 16|p7| + 16|p6| + 8|p5| + 4|p4| + 2|p3| + |p2|. if wfq sc heduling is used, n equals |p7| + |p6| + |p5| + |p4| + |p3| + |p2|. each drop level has defined high-drop and low-drop percentages, which indicate the percentage of high-drop and low-drop packets that will be dropped at th at level. the x, y, and z percent parameters can be programmed using the registers rdrc0 and rdrc1. parame ters a-f are the byte count thresholds for each priority queue, and are also programmable. when us ing delay bound scheduling, the values selected for a-f also control the approximate bandwidth partition among the traffic classes; see application note. 7.8 buffer management because the number of frame data buffer (fdb) slots is a scarce resource, and because we want to ensure that one misbehaving source port or class cannot harm the per formance of a well-behaved source port or class, we introduce the concept of buffer management into t he mvtx2804. our buffer management scheme is designed to divide the total buffer space into numerous reserved regions and one shared pool, (see figure 4). as shown in the figure, the fdb pool is divided into several parts. a reserved region for temporary frames stores frames prior to receiving a switch response. such a temporary region is necessary, because when the frame first enters the mvtx 2804, its destination port and class are as yet unknown, and so the decision to drop or not needs to be temporarily postponed. this ensures that every frame can be rece ived first before subjecting it to the frame drop discipline after classifying. six reserved sections, one for each of the highest six pr iority classes, ensure a programmable number of fdb slots per class. the lowest two classes do not receive any buffer reservation. another segment of the fdb reserves space for each of the 8 gigabit ports and cpu port. these source port buffer reservations are programmable. these 9 reserv ed regions make sure that no well-behaved source port can be blocked by another misbehaving source port. in addition, there is a shared pool, which can store any type of frame. the registers related to the buffer management logic are ? prg- port reservation for gigabit ports and cpu port ? sfcb- share fcb size ? c2rs- class 2 reserved size ? c3rs- class 3 reserved size ? c4rs- class 4 reserved size p7 p6 p5 p4 p3 p2 high drop low drop level 1 n 240 ? p7 ? a kb ? p6 ? b kb ? p5 ? c kb ? p4 ? d kb ? p3 ? e kb ? p2 ? f kb x% 0% level 2 n 280 y% z% level 3 n 320 100% 100% table 3 - wred dropping scheme
mvtx2804 data sheet 33 zarlink semiconductor inc. ? c5rs- class 5 reserved size ? c6rs- class 6 reserved size ? c7rs- class 7 reserved size figure 5 - buffer partition scheme used in the mvtx2804 7.8.1 dropping when buffers are scarce the following is a summary of the two examples of local dropping discussed earlier in this chapter: ? if a queue is a delay-bounded queue, we have a multi-le vel wred drop scheme, designed to control delay and partition bandwidth in case of congestion. ? if a queue is a wfq-scheduled queue, we have a mult i-level wred drop scheme, designed to prevent congestion. in addition to these reasons for dropping, the mvtx2804 also drops frames when global buffer space becomes scarce. the function of buffer management is to ensure t hat such droppings cause as little blocking as possible. 7.9 flow control basics because frame loss is unacceptable for some applications , the mvtx2804 provides a flow control option. when flow control is enabled, scarcity of buffer space in the sw itch may trigger a flow control signal; this signal tells a source port, sending a packet to this switch, to temporarily hold off. while flow control offers the clear benefit of no packet lo ss, it also introduces a problem for quality of service. when a source port receives an ethernet flow control si gnal, all microflows originati ng at that port, well-behaved or not, are halted. a single packet destined for a co ngested output can block other packets destined for uncongested outputs. the resulting head-of-line blocki ng phenomenon means that quality of service cannot be assured with high confidence when flow control is enabled. in the mvtx2804, each source port can independently have flow control enabled or di sabled. for flow control enabled ports, by default all frames are treated as lowest priority during transmissi on scheduling. this is done so that those frames are not exposed to the wred dr opping scheme. frames from flow control enabled ports temporary reservation r tmp per-source reservations 8-r 1g per-class r p7 , r p6 ,...r p2 shared pool s reservations
mvtx2804 data sheet 34 zarlink semiconductor inc. feed to only one queue at the destination, the queue of lowest priority. what this means is that if flow control is enabled for a given source port, then we can guarantee that no packets originating from that port will be lost, but at the possible expense of minimum bandwidth or ma ximum delay assurances. in addition, these ?downgraded? frames may only use the shared pool or the per-source re served pool in the fdb; frames from flow control enabled sources may not use reserved fdb sl ots for the highest six classes (p2-p7). the mvtx2804 does provide a system-wide option of pe rmitting normal qos scheduling (and buffer use) for frames originating from flow control enabled ports. when this programmable option is active, it is possible that some packets may be dropped, even though flow control is on. the reason is that intelligent packet dropping is a major component of the mvtx2804's approach to ensuring bounded delay and minimum bandwidth for high priority flows. 7.9.1 unicast flow control for unicast frames, flow control is triggered by source port resource availability. recall that the mvtx2804's buffer management scheme allocates a reserved number of fdb slots for each source port. if a programmed number of a source port's reserved fdb slots have be en used, then flow control xoff is triggered. xon is triggered when a port is currently being flow controlled , and all of that port's reserved fdb slots have been released. note that the mvtx2804's per-source-port fdb reservati ons assure that a source port that sends a single frame to a congested destination will not be flow controlled. 7.9.2 multicast flow control in unmanaged mode, a global buffer counter triggers flow control for multicast frames. when the system exceeds a programmable threshold of multicast packets, xoff is triggered. xon is triggered when the system returns below this threshold. mcc register programs the threshold. in managed mode, per-vlan flow control is used for multicas t frames. in this case, flow control is triggered by congestion at the destination. the mvtx2804 checks eac h destination to which a multicast packet is headed. for each destination port, the occupancy of the lowe st-priority transmission queue (measured in number of frames) is compared against a programmable congestion thre shold. if congestion is detected at even one of the packet's destinations, then xoff is triggered. in addition, each source port has an 8-bit port map record ing which port or ports of the multicast frame's fanout were congested at the time xoff was triggered. all por ts are continuously monitored for congestion, and a port is identified as uncongested when its queue occupancy falls below a fixed threshold. when all those ports that were originally marked as congested in the port map have become unc ongested, then xon is triggered, and the 8-bit vector is reset to zero. the mvtx2804 also provides the option of disabling multicast flow control. note : if port flow control is on, qos performance will be affected. 7.10 mapping to ietf diffserv classes the mapping between priority classes discussed in this chapter and elsewhere is shown below. as the table illustrates, p7 is used solely for network management (nm) frames. p6 is used for expedited forwarding service (ef). classes p2 through p5 correspond to an assured forwarding (af) group of size 4. finally, p0 and p1 are two best effort (be) classes. mvtx2804 p7 p6 p5 p4 p3 p2 p1 p0 ietf nm ef af0 af1 af2 af3 be0 be1 table 4 - mapping between mvtx2804 and ietf diffserv classes for gigabit ports
mvtx2804 data sheet 35 zarlink semiconductor inc. features of the mvtx2804 that correspond to the requirements of their associated ietf classes are summarized in the table below. 8.0 port trunking 8.1 features and restrictions a port group (i.e. trunk) can include up to 8 physical ports, but all of the ports in a group must be in the same mvtx2804. in managed mode, there are four trunk groups total. in unmanaged mode, the mvtx2804 provides several pr e-assigned trunk group options, containing as many as 4 ports per group, or alternatively, as many as 4 total groups. load distribution among the ports in a trunk for uni cast is performed using hashing based on source mac address and destination mac address. the other options include source mac address only, destination mac address only. load distribution for multicast is performed similarly. if a vlan includes any of the ports in a trunk group, all the ports in that trunk group should be in the same vlan member map. the mvtx2804 also provides a safe fail-over mode for port trunking automatically. if one of the ports in the trunking group goes down, the mvtx2804 will automatically redistribute the traffic over to the remaining ports in the trunk in unmanaged mode. in managed mode, the software can perform similar tasks. 8.2 unicast packet forwarding the search engine finds the destination mct entry, and if the status field says that the destination address found belongs to a trunk, then the group number is retrieved instead of the port number. in addition, if the source address belongs to a trunk, then the source port's trunk membership register is checked to determine if the address has moved. a hash key is used to determine the appropriate forwarding port, based on some combination of the source and destination mac addresses for the current packet. network management (nm) and expedited forwarding (ef) ? global buffer reservation for nm and ef ? shaper for ef traffic ? option of strict priority scheduling ? no dropping if admission controlled assured forwarding (af) ? four af classes ? programmable bandwidth partition, with option of wfq service ? option of delay-bounded service keeps delay under fixed levels even if not admission-controlled ? random early discard, with programmable levels ? global buffer reservation for each af class best effort (be) ? two be classes ? service only when other queues are idle means that qos not adversely affected ? random early discard, with programmable levels ? traffic from flow control enabled por ts automatically classified as be figure 6 - mvtx2804 features enabling ietf diffserv standards
mvtx2804 data sheet 36 zarlink semiconductor inc. the search engine retrieves the vlan member ports from the vlan index table, which consists of 4k entries. the search engine retrieves the vlan member ports from the ingress port's vlan map. based on the destination mac address, the search engine determines th e egress port from the mct database. if the egress port is a member of a trunk group, the packet can be di stributed to the other members of that trunk group. the vlan map is used to check whether the egress port is a member of the vlan, based on the ingress port. if it is a member, the packet is forwarded otherwise it is discarded. 8.3 multicast packet forwarding for multicast packet forwarding, the device must determine the proper set of ports from which to transmit the packet based on the vlan index and hash key. two functions are required in order to distribute multicast packets to the appropriate destination ports in a port trunking environment. ? determining one forwarding port per group. ? for multicast packets, all but one port per group, the forwarding port, must be excluded. 8.4 preventing multicast packets from looping back to the source trunk the search engine needs to prevent a multicast packet from sending to a port that is in the same trunk group with the source port. this is because, when we select the primary forwarding port for each group, we do not take the source port into account. to prevent this, we simply apply one additional filter, so as to block that forwarding port for this multicast packet. 9.0 led interface 9.1 introduction the mvtx2804 led block provides two interfaces: a se rial output channel, and a parallel time-division interface. the serial output channel provides port st atus information from the mvtx2804 chip in a continuous serial stream. this means that a low cost external devi ce must be used to decode the serial data and to drive an led array for display. by contrast, the parallel time-divis ion interface supports a glueless led m odule. indeed, the parallel interface can directly drive low-current leds wit hout any extra logic. the pin led_pm is used to select serial or parallel mode. for some led signals, the interface also provides a bl inking option. blinking may be enabled for led signals txd, rxd, col, and fc (to be described later). the pi n led_blink is used to enable blinking, and the blinking frequency is around 160 ms. 9.2 serial mode in serial mode, the following pins are utilized: ? led_synco - a sync pulse that defines the boundary between status frames ? led_clko - the clock signal ? led_do - a continuous serial stream of data for all status leds that repeats once every frame time in each cycle (one frame of status information, or one sync pulse), 16x8 bits of data are transmitted on the led_do signal. the sequence of transmission of data bits is as shown in the figure below:
mvtx2804 data sheet 37 zarlink semiconductor inc. figure 7 - timing diagram for se rial mode in led interface the status bits shown in here are flow control (fc), tran smitting data (txd), receiving data (rxd), link up (lnk), speed (sp0 and sp1), full duplex (fdx ), and collision (col). note that sp[1:0] is defined as 10 for 1 gbps, 01 for 100 mbps, and 00 for 10 mbps. also note that u0-u7 represent user-defined sub-fr ames in which additional status information may be embedded. we will see later that the mvtx2804 provides registers that can be written by the cpu to indicate this additional status informati on as it becomes available. 9.3 parallel mode in parallel mode, the foll owing pins are utilized: ? led_port_sel[9:0] - indicates which of the 8 gigabit por t status bytes or 2 user-defined status bytes is being read out ? led_byteout_[7:0] - provides 8 bits for 8 different por t status indicators. note that these bits are active low. by default, the system is in parallel mode. in para llel mode, the 10 status bytes are scanned in a continuous loop, with one byte read out per clock cycle, and the appropriate port select bit asserted. 9.4 led control registers an led control register can be used for programming t he led clock rate, sample hold time, and pattern in parallel mode. in addition, the mvtx2804 provides 8 registers called leduser[7:0] for user-defined status bytes. during operation, the cpu can write values to these registers, which will be read out to the led interface output (serial or parallel). only leduser[1:0] are used in parallel m ode. the content of the ledu ser registers will be sent out by the led serial shift logic, or in parallel mode, a byte at a time. because in parallel mode there are only two user-defi ned registers, leduser[7:2] is shared with ledsig[7:2]. for ledsig[j], where j = 2, 3, ?, 6, the corres ponding register is used for programming the led pin led_byteout_[j]. the format is as follows: bits [3:0]signal polarity: 0: do not invert polarity (high true) 1: invert polarity 743 0 col fdx sp1 sp0 col fdx sp1 sp0 p0 info p1 info p2 info p3 info p4 info p5 info p6 info p7 info u0 u1 u2 u3 u4 u5 u6 u7 le_synco le_do le_clko fc txd rxd lnk sp0 sp1 fdx col 07 6 5 4 3 2 1
mvtx2804 data sheet 38 zarlink semiconductor inc. bits [7:4]signal select: 0: do not select 1: select the corresponding bit for j = 2, 3, ?, 5, the value of le d_byteout_[j] equals the logical and of all selected bits. for j = 6, the value is equal to the logical or. therefore, the programmable ledsig[5:2] registers allow any conjunctive formula including any of the 4 status bits (col, fdx, sp1, sp0) or their negations to be sent to the led_byteout_[5:2] pins. similarly, the programmabl e ledsig[6] register allows any disjunctive formula including any of the 4 status bits or thei r negations to be sent to pin led_byteout_[6]. ledsig[7] is used for programming bot h led_byteout_[1] and led_byteout_[0]. as we will see, it has other functions as well. the format is as follows: 10.0 hardware statistics counter 10.1 hardware statistics counters list mvtx2804 hardware provides a full set of statistics counters for each et hernet port. the cpu accesses these counters through the cpu interface. all hardware counters are rollover counters. when a counter rolls over, the cpu is interrupted, so that long-term statistics may be kept. the mac detects all statistics, except for the delay exceed discard counter (detected by buffer manager) and the filtering counter (detected by queue manager). the following is the wrapped signal sent to the cpu through the command block. 743 0 gp rxd txd fc p6 rxd txd fc bits [7] ? global output polarity: this bit cont rols the output polarity of all led_byteout_ and led_port_sel pins. (default 0) - 0: do not invert polarity (led_byteout_[7:0] are high activated; led_port_sel[9:0] are low activated) - 1: invert polarity (led_byteout_[7:0] ar e low activated; led_port_sel[9:0] are high activated) bits [6:4] ? signal select: - 0: do not select - 1: select the corresponding bit ? the value of led_byteout_[1] equals th e logical or of all selected bits. (default 110) bit [3] ? polarity contro l of led_byteout_[6] (default 0) - 0: do not invert - 1: invert bits [2:0] ? signal select: - 0: do not select - 1: select the corresponding bit ? the value of led_byteout_[0] equals th e logical or of all selected bits. (default 001)
mvtx2804 data sheet 39 zarlink semiconductor inc. b[0] 0-d bytes sent (d) b[1] 1-l unicast frame sent b[2] 1-u frame send fail b[3] 2-i flow control frames sent b[4] 2-u non-unicast frames sent b[5] 3-d bytes received (good and bad) (d) b[6] 4-d frames received (good and bad) (d) b[7] 5-d total bytes received (d) b[8] 6-l total frames received b[9] 6-u flow control frames received b[10] 7-l multicast frames received b[11] 7-u broadcast frames received b[12] 8-l frames with length of 64 bytes b[13] 8-u jabber frames b[14] 9-l frames with length between 65-127 bytes b[15] 9-u oversize frames b[16] a-l frames with length between 128-255 bytes b[17] a-u frames with length between 256-511 bytes b[18] b-l frames with length between 512-1023 bytes b[19] b-u frames with length between 1024-1528 bytes b[20] c-l fragments b[21] c-u1 alignment error b[22] c-u undersize frames b[23] d-l crc b[24] d-u short event b[25] e-l collision b[26] e-u drop b[27] f-l filtering counter b[28] f-u1 delay exceed discard counter b[29] f-u late collision b[30] link status change b[31] current link status notation: x-y x: address in the contain memory y: size and bits for the counter d: d word counter l: 24 bits counter bit[23:0] u: 8 bits counter bit[31:24] u1: 8 bits counter bit[23:16] l: 16 bits counter bit[15:0] u: 16 bits counter bit[31:16] 31 30 26 25 0 status wrapped signal
mvtx2804 data sheet 40 zarlink semiconductor inc. 10.2 ieee 802.3 hub mana gement (rfc 1213) 10.2.1 event counters 10.2.1.1 readableoctet counts number of bytes (i.e. octets) contained in good valid frames received. frame size: 64 bytes,< 1522 bytes if vlan tagged; 1518 bytes if not vlan tagged no fcs (i.e. checksum) error no collisions 10.2.1.2 readableframe counts number of good valid frames received. frame size: 64 bytes,< 1522 bytes if vlan tagged; 1518 bytes if not vlan tagged no fcs error no collisions 10.2.1.3 fcserrors counts number of valid frames received with bad fcs. frame size: 64 bytes, 1522 bytes if vlan tagged; 1518 bytes if not vlan tagged no framing error no collisions 10.2.1.4 alignmenterrors counts number of valid frames received with bad alignment (not byte-aligned). frame size: 64 bytes, 1522 bytes if vlan tagged; 1518 bytes if not vlan tagged no framing error no collisions 10.2.1.5 frametoolongs counts number of frames received with size exceeding the maximum allowable frame size. frame size: 64 bytes, 1522 bytes if vlan tagged; 1518 bytes if not vlan tagged fcs error:don't care
mvtx2804 data sheet 41 zarlink semiconductor inc. framing error:don't care no collisions 10.2.1.6 shortevents counts number of frames received with size less than the length of a short event. frame size: 64 bytes, 10 bytes fcs error:don't care framing error:don't care no collisions 10.2.1.7 runts counts number of frames received with size under 64 by tes, but greater than the length of a short event. frame size: 10 bytes, 64 bytes fcs error:don't care framing error:don't care no collisions 10.2.1.8 collisions counts number of collision events. frame size:any size 10.2.1.9 lateevents counts number of collision events that occurred late (after lateeventthreshold = 64 bytes). frame size:any size events are also counted by collision counter 10.2.1.10 verylongevents counts number of frames received with size larger than jabber lockup protection timer (tw3). frame size:> jabber 10.2.1.11 dataratemisatches for repeaters or hub application only. 10.2.1.12 autopartitions for repeaters or hub application only.
mvtx2804 data sheet 42 zarlink semiconductor inc. 10.2.1.13 totalerrors sum of the following errors: fcs errors alignment errors frame too long short events late events very long events 10.3 ieee - 802.1 bri dge management (rfc 1286) 10.3.0.1 event counters 10.3.0.2 inframes counts number of frames received by this port or segment. note : this counter only counts a frame received by this port if and only if it is for a protocol being processed by the local bridge function. 10.3.0.3 outframes counts number of frames transmitted by this port. note : this counter only counts a frame transmitted by this por t if and only if it is for a protocol being processed by the local bridge function. 10.3.0.4 indiscards counts number of valid frames received which were di scarded (i.e., filtered) by the forwarding process. 10.3.0.5 delayexceededdiscards counts number of frames discarded due to excessive transmit delay through the bridge. 10.3.0.6 mtuexceededdiscards counts number of frames discarded due to excessive size. 10.4 rmon - ethernet statistic group (rfc 1757) 10.4.1 event counters 10.4.1.1 drop events counts number of times a packet is dropped, because of lack of available resources. does not include all packet dropping -- for example, random early drop for quality of service support.
mvtx2804 data sheet 43 zarlink semiconductor inc. 10.4.1.2 octets counts the total number of octets (i.e. bytes) in any frames received. 10.4.1.3 broadcastpkts counts the number of good frames received and forwarded with broadcast address. does not include non-broadcast multicast frames. 10.4.1.4 multicastpkts counts the number of good frames received and forwarded with multicast address. does not include broadcast frames. 10.4.1.5 crcalignerrors frame size: 64 bytes,< 1522 bytes if vlan tag (1518 if no vlan) no collisions: counts number of frames received with fcs or alignment errors 10.4.1.6 undersizepkts counts number of frames received with size less than 64 bytes. frame size:< 64 bytes, no fcs error no framing error no collisions 10.4.1.7 oversizepkts counts number of frames received with size exceeding the maximum allowable frame size. frame size:>1522 bytes if vlan tag (1518 bytes if no vlan) fcs errordon't care framing errordon't care no collisions 10.4.1.8 fragments counts number of frames received with size less than 64 bytes and with bad fcs. frame size:< 64 bytes framing error don't care no collisions
mvtx2804 data sheet 44 zarlink semiconductor inc. 10.4.1.9 jabbers counts number of frames received with size exceeding maximum frame size and with bad fcs. frame size:> 1522 bytes if vlan tag (1518 bytes if no vlan) framing errordon't care no collisions 10.4.1.10 collisions counts number of collision events detected. only a best estimate since collisions can only be detected while in transm it mode, but not while in receive mode. frame size:any size 10.4.1.11 packet count for different size groups six different size groups - one counter for each: pkts64octetsfor any packet with size = 64 bytes pkts65to127octetsfor any packet with size from 65 bytes to 127 bytes pkts128to255octetsfor any packet with size from 128 bytes to 255 bytes pkts256to511octetsfor any packet with size from 256 bytes to 511 bytes pkts512to1023octetsfor any packet with size from 512 bytes to 1023 bytes pkts1024to1518octetsfor any packet with size from 1024 bytes to 1518 bytes counts both good and bad packets. miscellaneous counters in addition to the statistics groups defined in previous sections, the mvtx2804 has other statistics counters for its own purposes. we have two counters for flow contro l - one counting the number of flow control frames received, and another counting the number of flow cont rol frames sent. we also have two counters, one for unicast frames sent, and one for non-unicast frames sent. a broadcast or multicast frame qualifies as non-unicast. furthermore, we have a counter called ?frame send fail.? this keeps track of fifo under-runs, late collisions, and collisions that have occurred 16 times.
mvtx2804 data sheet 45 zarlink semiconductor inc. 11.0 regi ster definition 11.1 register description register description table register description cpu addr (hex) r/w i 2 c addr (hex) default notes 0. ethernet port control registers - substitute [n] with port number (0..7) ecr1p"n" port control register 1 for port n (n=0-7) 000 + 2n r/w 000+2n c0 ecr2p"n" port control register 2 for port n (n=0-7) 001 + 2n r/w 001+2n 00 ecrmisc1 port control misc1 010 r/w 010 c0 ecrmisc2 port control misc 2 011 r/w 011 00 ggcontrol0 extra gigabit port control -port 0,1 012 r/w n/a 00 ggcontrol1 extra gigabit port control -port 2,3 013 r/w n/a 00 ggcontrol2 extra gigabit port control -port 4,5 014 r/w n/a 00 ggcontrol3 extra gigabit port control -port 6,7 015 r/w n/a 00 activelink active link status port 7:0 016 r/w n/a 00 1. vlan control registers - substitute [n] with port number (0..8) avtcl vlan type code register low 100 r/w 012 00 avtch vlan type code register high 101 r/w 013 81 pvmap"n"_0 port "n" configuration register 0 (n=0-8) 102 + 4n r/w 014+4n ff pvmap"n"_1 port "n" configuration register 1 (n=0-8) 103 + 4n r/w 015+4n ef pvmap"n"_3 port "n" configuration register 3 (n=0-8) 105 + 4n r/w 017+4n 00 pvmode vlan operating mode 126 r/w 038 00 2. trunk control registers trunk0 trunk group 0 member 200 r/w na 00 trunk1 trunk group 1 member 201 r/w na 00 trunk2 trunk group 2 member 202 r/w na 00 trunk3 trunk group 3 member 203 r/w na 00 single_ring single ring port map 204 r/w na reserved trunk_ring trunk ring port map 205 r/w na reserved trunk_hash_mode trunk hash mode 206 r/w na 00 trunk0_mode trunk group 0 mode 207 r/w 039 00
mvtx2804 data sheet 46 zarlink semiconductor inc. trunk0_hash0 trunk group 0 hash 0, 1, 2 destination port 208 r/w na 08 trunk0_hash1 trunk group 0 hash 2, 3, 4, 5 destination port 209 r/w na 82 trunk0_hash2 trunk group 0 hash 5, 6, 7 destination port 20a r/w na 20 trunk0_hash3 trunk group 0 hash 8, 9, 10 destination port 20b r/w na 08 trunk0_hash4 trunk group 0 hash 10, 11, 12, 13 destination port 20c r/w na 82 trunk0_hash5 trunk group 0 hash 13, 14, 15 destination port 20d r/w na 20 trunk1_mode trunk group 1 mode 20e r/w 03a 00 trunk1_hash0 trunk group 1 hash 0, 1, 2 destination port 20f r/w na 08 trunk1_hash1 trunk group 1 hash 2, 3, 4, 5 destination port 210 r/w na 82 trunk1_hash2 trunk group 1 hash 5, 6, 7 destination port 211 r/w na 20 trunk1_hash3 trunk group 1 hash 8, 9, 10 destination port 212 r/w na 08 trunk1_hash4 trunk group 1 hash 10, 11, 12, 13 destination 213 r/w na 82 trunk1_hash5 trunk group 1 hash 13, 14, 15 destination 214 r/w na 20 trunk2_hash0 trunk group 2 hash 0, 1, 2 destination port 215 r/w na 2c trunk2_hash1 trunk group 2 hash 2, 3, 4, 5 destination port 216 r/w na cb trunk2_hash2 trunk group 2 hash 5, 6, 7 destination port 217 r/w na b2 trunk2_hash3 trunk group 2 hash 8, 9, 10 destination port 218 r/w na 2c trunk2_hash4 trunk group 2 hash 10, 11, 12, 13 destination port 219 r/w na cb trunk2_hash5 trunk group 2 hash 13, 14, 15 destination port 21a r/w na b2 trunk3_hash0 trunk group 3 hash 0, 1, 2 destination port 21b r/w na 2c trunk3_hash1 trunk group 3 hash 2, 3, 4, 5 destination port 21c r/w na cb trunk3_hash2 trunk group 3 hash 5, 6, 7 destination port 21d r/w na b2 register description table (continued) register description cpu addr (hex) r/w i 2 c addr (hex) default notes
mvtx2804 data sheet 47 zarlink semiconductor inc. trunk3_hash3 trunk group 3 hash 8, 9, 10 destination port 21e r/w na 2c trunk3_hash4 trunk group 3 hash 10, 11, 12, 13 destination port 21f r/w na bc trunk3_hash5 trunk group 3 hash 13, 14, 15 destination port 220 r/w na b2 multicast_hash00 multicast hash result 0 mask bit[7:0] 221 r/w na ff multicast_hash01 multicast hash result 1 mask bit[7:0] 222 r/w na ff multicast_hash02 multicast hash result 2 mask bit[7:0] 223 r/w na ff multicast_hash03 multicast hash result 3 mask bit[7:0] 224 r/w na ff multicast_hash04 multicast hash result 4 mask bit[7:0] 225 r/w na ff multicast_hash05 multicast hash result 5 mask bit[7:0] 226 r/w na ff multicast_hash06 multicast hash result 6 mask bit[7:0] 227 r/w na ff multicast_hash07 multicast hash result 7 mask bit[7:0] 228 r/w na ff multicast_hash08 multicast hash result 8 mask bit[7:0] 229 r/w na ff multicast_hash09 multicast hash result 9 mask bit[7:0] 22a r/w na fff multicast_hash10 multicast hash result 10 mask bit[7:0] 22b r/w na ff multicast_hash11 multicast hash result 11 mask bit[7:0] 22c r/w na ff multicast_hash12 multicast hash result 12 mask bit[7:0] 22d r/w na ff multicast_hash13 multicast hash result 13 mask bit[7:0] 22e r/w na ff multicast_hash14 multicast hash result 14 mask bit[7:0] 22f r/w na ff multicast_hash15 multicast hash result 15 mask bit[7:0] 230 r/w na ff multicast_hashml multicast hash bit[8] for result 7-0 231 r/w na ff multicast_hashmh multicast hash bit[8] for result 15-8 232 r/w na ff register description table (continued) register description cpu addr (hex) r/w i 2 c addr (hex) default notes
mvtx2804 data sheet 48 zarlink semiconductor inc. 3. cpu port configuration mac0 cpu mac address byte 0 300 r/w na 00 mac1 cpu mac address byte 1 301 r/w na 00 mac2 cpu mac address byte 2 302 r/w na 00 mac3 cpu mac address byte 3 303 r/w na 00 mac4 cpu mac address byte 4 304 r/w na 00 mac5 cpu mac address byte 5 305 r/w na 00 int_mask0 interrupt mask 0 306 r/w na ff int_mask1 interrupt mask 1 307 r/w na ff int_mask2 interrupt mask 2 308 r/w na ff int_mask3 interrupt mask 3 309 r/w na ff int_status0 status of masked interrupt register0 30a ro na int_status1 status of masked interrupt register1 30b ro na intp_mask"n" interrupt mask for mac port 2n, 2n+1 ( n=0-3) 30c-30f r/w na ff rqs receive queue select 310 r/w na 00 rqss receive queue status 311 ro na tx_age transmission queue aging time 312 r/w 03b 08 4. search engine configurations agetime_low mac address aging time low 400 r/w 03c 2c agetime_high mac address aging time high 401 r/w 03d 00 v_agetime vlan to port aging time 402 r/w na ff se_opmode search engine operation mode 403 r/w na 00 scan scan control register 404 r/w na 00 5. buffer control and qos control fcbat fcb aging timer 500 r/w 03e ff qosc qos control 501 r/w 03f 00 fcr flooding control register 502 r/w 040 08 avpml vlan priority map low 503 r/w 041 88 avpmm vlan priority map middle 504 r/w 042 c6 avpmh vlan priority map high 505 r/w 043 fa tospml tos priority map low 506 r/w 044 88 tospmm tos priority map middle 507 r/w 045 c6 tospmh tos priority map high 508 r/w 046 fa avdm vlan discard map 509 r/w 047 00 tosdml tos discard map 50a r/w 048 00 register description table (continued) register description cpu addr (hex) r/w i 2 c addr (hex) default notes
mvtx2804 data sheet 49 zarlink semiconductor inc. bmrc broadcast/multicast rate control 50b r/w 049 00 ucc unicast congestion control 50c r/w 04a 07 mcc multicast congestion control 50d r/w 04b 48 pr100 port reservation for 10/100 ports 50e r/w 04c 00 prg port reservation for giga ports 50f r/w 04d 26 sfcb share fcb size 510 r/w 04e 37 c2rs class 2 reserved size 511 r/w 04f 00 c3rs class 3 reserved size 512 r/w 050 00 c4rs class 4 reserved size 513 r/w 051 00 c5rs class 5 reserved size 514 r/w 052 00 c6rs class 6 reserved size 515 r/w 053 00 c7rs class 7 reserved size 516 r/w 054 00 qosc"n" qos control (n=0 - 2f) 517-546 r/w 055-084 qosc"n" qos control (n=30 - 82) 547-599 r/w na rdrc0 wred rate control 0 59a r/w 085 8e rdrc1 wred rate control 1 59b r/w 086 68 6. misc configuration registers mii_op0 mii register option 0 600 r/w 0b1 00 mii_op1 mii register option 1 601 r/w 0b2 00 fen feature registers 602 r/w 0b3 10 miic0 mii command register 0 603 r/w n/a 00 miic1 mii command register 1 604 r/w n/a 00 miic2 mii command register 2 605 r/w n/a 00 miic3 mii command register 3 606 r/w n/a 00 miid0 mii data register 0 607 ro n/a 00 miid1 mii data register 1 608 ro n/a 00 led led control register 609 r/w 0b4 38 checksum eeprom checksum register 60b r/w 0c5 00 leduser0 led user define register 0 60c r/w 0bb 00 leduser1 led user define register 1 60d r/w 0bc 00 leduser2 led user define reg. 2/led_byte pin 2 60e r/w 0bd 80 leduser3 led user define reg. 3/led_byte pin 3 60f r/w 0be 33 leduser4 led user define reg. 4/led_byte pin 4 610 r/w 0bf 32 leduser5 led user define reg. 5/led_byte pin 5 611 r/w 0c0 20 register description table (continued) register description cpu addr (hex) r/w i 2 c addr (hex) default notes
mvtx2804 data sheet 50 zarlink semiconductor inc. leduser6 led user define reg. 6/led_byte pin 6 612 r/w 0c1 40 leduser7 led user define reg. 7/led_byte pin 1 & 0 613 r/w 0c2 61 miinp0 mii next page data register0 614 r/w 0c3 00 miinp1 mii next page data register1 615 r/w 0c4 00 e. test group control dtsrl test register low e00 r/w n/a 00 dtsrm test register medium e01 r/w n/a 01 dtsrh test register high e02 r/w n/a 00 tdrb0 test mux read back register [7:0] e03 ro n/a tdrb1 test mux read back register [15:8] e04 ro n/a dtcr test counter register e05 r/w n/a 00 mask0 mask timeout 0 e06 r/w 0b6 00 mask1 mask timeout 1 e07 r/w 0b7 00 mask2 mask timeout 2 e08 r/w 0b8 00 mask3 mask timeout 3 e09 r/w 0b9 00 mask4 mask timeout 4 e0a r/w 0ba 00 f. device configuration register gcr global control register f00 r/w n/a 00 dcr device status and signature register f01 ro n/a dcr01 gigabit port0 port1 status register f02 ro na dcr23 gigabit port2 port3 status register f03 ro na dcr45 gigabit port4 port5 status register f04 ro na dcr67 gigabit port6 port7 status register f05 ro na dpst device port status register f06 r/w n/a 00 dtst data read back register f07 ro n/a pllcr pll control register f08 r/w n/a reserved lclkcr lclk control register f09 r/w n/a reserved bclkcr bclk control register f0a r/w n/a reserved register description table (continued) register description cpu addr (hex) r/w i 2 c addr (hex) default notes
mvtx2804 data sheet 51 zarlink semiconductor inc. note 1: se = search engine note 2: fe = frame engine note 3: pgs = port group01, 23, 45, and 67 note 4: mc = mac control note 5: tm = timer 11.2 directly accessed registers 11.2.1 index_reg0 ? address bits [7:0] for indirectly accessed register addresses ? address = 0 (write only) 11.2.2 index_reg1 (only needed for cpu 8-bit bus mode) ? address bits [15:8] for indirectly accessed register addresses ? address = 1 (write only) 11.2.3 data_frame_reg ? data of indirectly accessed registers. (8 bits) ? address = 2 (read/write) 11.2.4 control_frame_reg ? cpu transmit/receive switch frames. (8/16 bits) ? address = 3 (read/write) ? format: (see processor interface application note for more information) - send frame from cpu: (in sequence) frame data (size should be in multiple of 8-byte) 8-byte of frame status (frame size, destination port #, frame o.k. status) - cpu received frame: (in sequence) bstrrb0 boot strap read back register 0 f0b ro n/a reserved bstrrb1 boot strap read back register 1 f0c ro n/a reserved bstrrb2 boot strap read back register 2 f0d ro n/a reserved bstrrb3 boot strap read back register 3 f0e ro n/a reserved bstrrb4 boot strap read back register 4 f0f ro n/a reserved bstrrb5 boot strap read back register 5 f10 ro n/a reserved da da register fff ro n/a da register description table (continued) register description cpu addr (hex) r/w i 2 c addr (hex) default notes
mvtx2804 data sheet 52 zarlink semiconductor inc. 8-byte of frame status (frame size, source port #, vlan tag) frame data 11.2.5 command & status ? cpu interface commands (write) and status ? address = 4 (read/write) ? when the cpu reads this register: - bit [0]: transmit control command 1 ready; must read true before cpu writes new control command 1. - bit [1]: receive control command 1 r eady; must read true before cpu reads a new control command 1. - bit [2]: receive control command 2 ready; must read true before cpu reads a new control command 2. - bit [3]: receive cpu frame ready; must read true before receiving a cpu frame and at every 8-byte boundary within a cpu frame. - bit [4]: transmit cpu frame ready; must read true before transmitting a cpu frame and at every 16-byte boundary within a cpu frame. - bit [5]: end of receive cpu frame to indicate that the last 8 bytes need to be read. - bit [15:6]: reserved. ? when the cpu writes to this register: - bit [0]: end of transmit control command indicator; set af ter cpu writes a control command frame into rx buffer. - bit [1]: end of receive control command 1 indicator; set after cpu reads out a control command 1 frame from tx buffer 1. - bit [2]: end of receive control command 2 indicator; set after cpu reads out a control command 2 frame from tx buffer 2. - bit [3]: end of receive cpu frame indi cator. set after cpu reads out a cpu frame or to flush out the rest of cpu frame. - bit [4]: end of transmit cpu frame indicator. se t before writing the last byte of cpu frame. - bit [7:5]: reserved and always write 0's. - bit [15:8]: reserved and write 0's in 16-bit mode. 11.2.6 interrupt register ? interrupt sources (8 bits) ? address = 5 (read only) ? when cpu reads this register bit [0]: cpu frame interrupt bit [1]:control frame 1 interrupt. control fram e receive buffer1 has data for cpu to read bit [2]:control frame 2 interrupt. control fram e receive buffer2 has data for cpu to read bit [3]from any of the gigabit port interrupt bit [7:4]:reserve note : this register is not self-cleared. after re ading cpu has to clear the bit writing 0 to it
mvtx2804 data sheet 53 zarlink semiconductor inc. 11.2.7 control frame buffer1 access register ? address = 6 (read/write) ? when cpu writes to this register, data is written to the control command frame receive buffer ? when cpu reads this register, data is read from the control command frame transmit buffer1 11.2.8 control frame buffer2 access register ? address = 7 (read only) ? when cpu reads this register, data is read from the control command frame transmit buffer 2 indirectly accessed registers 11.3 group 0 address 11.3.1 mac ports group 11.3.1.1 ecr1pn: port n control register ?i 2 c address h00+2n; cpu address:h000+2n (n=0 to 7) ? accessed by cpu, serial interface and i 2 c (r/w) 7654321 0 sp state a-fc port mode bit [4:0] ? port mode (default 2'b00) bit [4:3] ? 00 - automatic enable auto-negotiation - this enables hardware state machine for auto-negotiation. ? 01 - limited disable auto-negotiation - this disables hardware auto-negotiation. hardware only polls mii for link status. us e bit [2:0] for config. ? 10 - link down - force link down (disable the port). does not talk to phy. ? 11 - link up - does not talk to phy. user erc1 [2:0] for config. bit [2] ? 1 - 10mbps (default 1'b0) ? 0 - 100mbps bit 2 is used only when the port is in mii mode. bit [1] ? 1 - half duplex (do not use) (default 1'b0) ? 0 - full duplex bit [0] ? 1 - flow control off (default 1'b0) ? 0 - flow control on ? when flow control is on: ? in full duplex mode, the mac transmitter sends flow control frames when necessary. the mac receiver interprets and processes incoming flow control frames. the flow control frame received counter is incremented whenever a flow control frame is received. ? when flow control is off: ? in full duplex mode, the mac transmitter does not send flow control frames. the mac receiver does not interpret or process the flow control frames. the flow control frame receiver counter is not incremented.
mvtx2804 data sheet 54 zarlink semiconductor inc. 11.3.1.2 ecr2pn: port n control register ?i 2 c address: 01+2n; cpu address:h001+2n (n=0to7) ? accessed by cpu and serial interface (r/w): bit [5] ? asymmetric flow control enable. ? 0 - disable asymmetric flow control ? 1 - enable asymme tric flow control ? when this bit is set, and flow control is on (bit[0] = 0), don't send out a flow control frame. but mac receiver interprets and process flow control frames. (default is 0) bit [7:6] ? ss - spanning tree state (802.1d spanning tree protocol). (default 2'b11) ? 00 - blocking: frame is dropped ? 01 - listening: frame is dropped ? 10 - learning: frame is dropped. source mac address is learned. ? 11 - forwarding: frame is forwarded. source mac address is learned. 7653210 security en disl ftf futf bit[0] ? filter untagged frame (default 0) ? 0: disable ? 1: enable - all untagged frames from this port are discarded or follow security op tion when security is enable bit[1] ? filter tag frame (default 0) ?0: disable ? 1: enable - all tagged frames from this port are discarded or follow securi ty option when security is enable bit[2] ? learning disable (default 0) ? 0: learning is enabled on this port ? 1: learning is disabled on this port bit [5:3:] ? reserved bit[7:6] ? security enable (default 00). the mvtx2804 c hecks the incoming data for one of the following conditions: 1. if the source mac address of the incoming packet is in the mac table and is defined as secure address but the ingress port is not the same as the port associated with the mac address in the mac table. a mac address is defined as secure when its entry at mac table has static status and bit 0 is set to 1. mac address bit 0 (the first bit transmitt ed) indicates whether the address is unicast or multicast. as source addresses are always unica st bit 0 is not used (always 0). mvtx2804 uses this bit to define secure mac addresses. 2. if the port is set as learning disable and the source mac address of the incoming packet is not defined in the mac address table. 3. if the port is configured to filter untagged frames and an untagged frame arrives or if the port is configured to filter tagged frames and a tagged frame arrives. if one of these three conditions occurs, the packet will be handled according to one of the following specified options:
mvtx2804 data sheet 55 zarlink semiconductor inc. 11.3.1.3 ecrmisc1 - cpu port control register misc1 ?i 2 c address h10, cpu address:h010 ? access by cpu, serial interface and i 2 c (r/w) 11.3.1.4 ecrmisc2 - cpu port control register misc2 ?(i 2 c address h11, cpu address:h011) ? access by cpu, serial interface and i 2 c (r/w) ?cpu installed ? 00 - disable port security ? 01 - discard violating packets ? 10 - send packet to cpu and destination port ? 11 - send packet to cpu only ?cpu not installed ? 00 - disable port security ? 01 - enable port security. port will be disabled when security violation is detected ?10 - n/a ?11 - n/a 765 0 ss state reserved bit [5:0] ? reserved bit [7:6] ? ss - spanning tree state (802.1d spanning tree protocol). (default 2'b11) ? 00 - blocking: frame is dropped ? 01 - listening: frame is dropped ? 10 - learning: frame is dropped. source mac address is learned. ? 11 - forwarding: frame is forwarded. source mac address is learned. 765 3210 security en disl ftf futf bit [0] ? filter untagged frame (default 0) ?0: disable ? 1: enable - all untagged frames from the cpu are disca rded or follow se curity option wh en security is enable security does not make much sense for cpu! bit[1] ? filter tagged frame (default 0) ?0: disable ? 1: enable - all tagged frames from the cpu are disca rded or follow security option when security is enable security does not make much sense for cpu! bit[2] ? learning disable (default 0) ? 1 - learning is disabled on this port ? 0 - learning is enabled on this port bit [5:3] ? reserved (default 0) bit[7:6] ? security enable (default 2'b00)
mvtx2804 data sheet 56 zarlink semiconductor inc. 11.3.1.5 ggcontrol 0- extra giga port control ? cpu address:h012 ? accessed by cpu and serial interface (r/w) 11.3.1.6 ggcontrol 1- extra giga port control ? cpu address:h013 ? accessed by cpu and serial interface (r/w) ?cpu installed ? 00 - disable port security ? 01 - discard violation packet ? 10 - send packet to cpu and port ? 11 - send packet to cpu only 76543210 mii1 rst1 mii0 rst0 bit[0]: ? reset giga port 0 default is 0 ? 0: normal operation ? 1: reset gigabit port 0. example: used when a new why is connected (hot swap) bit[1]: ? giga port 0 use mii interface (10/100m) default is 0 ? 0: gigabit port operation at 1000m mode ? 1: gigabit port operation at 10/100m mode (mii) bit[3:2]: ? reserved - must be '0' bit[4]: ? reset giga port 1 default is 0 ? 0: normal operation ? 1: reset gigabit port 1. example: used when a new phy is connected (hot swap) bit[5]: ? giga port 1 use mii interface (10/100m) default is 0 ? 0: gigabit port operation at 1000m mode ? 1: gigabit port operation at 10/100m mode (mii) bit[7:6]: ? reserved - must be '0' 7 65 43 210 mii3 rst3 mii2 rst2 bit[0]: ? reset giga port 2 default is 0 ? 0: normal operation ? 1: reset gigabit port 2. example: used when a new phy is connected (hot swap) bit[1]: ? giga port 2 use mii interface (10/100m) default is 0 ? 0: gigabit port operation at 1000m mode ? 1: gigabit port operation at 10/100m mode (mii) bit[3:2]: ? reserved - must be '0' bit[4]: ? reset giga port 3 default is 0 ? 0: normal operation ? 1: reset gigabit port 3. example: used when a new phy is connected (hot swap)
mvtx2804 data sheet 57 zarlink semiconductor inc. 11.3.1.7 ggcontrol 2- extra giga port control ? cpu address:h014 ? accessed by cpu and serial interface (r/w) 11.3.1.8 ggcontrol 3- extra giga port control ? cpu address:h015 ? accessed by cpu and serial interface (r/w) bit[5]: ? giga port 3 use mii interface (10/100m) default is 0 ? 0: gigabit port operation at 1000m mode ? 1: gigabit port operation at 10/100m mode (mii) bit[7:6]: ? reserved - must be '0' 76543210 mii5 rst5 mii4 rst4 bit[0]: ? reset giga port 4 default is 0 ? 0: normal operation ? 1: reset gigabit port 4. example: used when a new phy is connected (hot swap) bit[1]: ? giga port 4 use mii interface (10/100m) default is 0 ? 0: gigabit port operation at 1000m mode ? 1: gigabit port operation at 10/100m mode (mii) bit[3:2]: ? reserved - must be '0 bit[4]: ? reset giga port 5 default is 0 ? 0: normal operation ? 1: reset gigabit port 5. example: used when a new phy is connected (hot swap) bit[5] ? giga port 5 use mii interface (10/100m) default is 0 ? 0: gigabit port operation at 1000m mode ? 1: gigabit port operation at 10/100m mode (mii) bit[7:6]: ? reserved - must be '0' 76543210 mii7 rst7 mii6 rst6 bit[0]: ? reset giga port 6 default is 0 ? 0: normal operation ? 1: reset gigabit port 6. example: used when a new phy is connected (hot swap) bit[1]: ? giga port 6 use mii interface (10/100m) default is 0 ? 0: gigabit port operation at 1000m mode ? 1: gigabit port operation at 10/100m mode (mii) bit[3:2]: ? reserved - must be '0 bit[4]: ? reset giga port 7 default is 0 ? 0: normal operation ? 1: reset gigabit port 7. example: used when a new phy is connected (hot swap)
mvtx2804 data sheet 58 zarlink semiconductor inc. 11.4 group 1 address 11.4.1 vlan group 11.4.1.1 avtcl - vlan type code register low ?i 2 c address h12; cpu address:h100 ? accessed by cpu, serial interface and i 2 c (r/w) bit[7:0]:vlantype_low: lower 8 bits of the vlan type code (default 00) 11.4.1.2 avtch - vlan type code register high ?i 2 c address h13; cpu address:h101 ? accessed by cpu, serial interface and i 2 c (r/w) bit [7:0] vlantype_high: upper 8 bits of the vlan type code (default is 81) 11.4.1.3 pvmap00_0 - port 00 configuration register 0 ?i 2 c address h14, cpu address:h102) ? accessed by cpu, serial interface and i 2 c (r/w) in port based vlan mode this register indicates the legal egress ports. example: a ?1? on bit 7 means that packets arriving on port 0 can be sent to port 7. a ?0? on bit 7 means that any packet destined to port 7 will be discarded. in tag based vlan mode this is the default vlan tag. it works with configur ation register pvmap00_1 [7:5] [3:0] to form the default vlan tag. if the received packed is untagged, it receives the default vlan tag. if the packet has a vlan id of 0, then pvid is used to replace the packet's vlan. 11.4.1.4 pvmap00_1 - port 00 configuration register 1 ?i 2 c address h15, cpu address:h103 ? accessed by cpu, serial interface and i 2 c (r/w) in port based vlan mode bit[5] ? giga port 7 use mii interface (10/100m) default is 0 ? 0: gigabit port operation at 1000m mode ? 1: gigabit port operation at 10/100m mode (mii) bit[7:6]: ? reserved - must be '0' bit[7:0]: vlan mask for ports 7 to 0 (default ff) 0 - disable 1 - enable bit[7:0]: pvid [7:0] (default is ff) bit[7:0]: vlan mask for port 8 - cpu port (default is ff)
mvtx2804 data sheet 59 zarlink semiconductor inc. in tag based vlan mode 11.4.1.5 pvmap00_3 - port 00 configuration register 3 ?i 2 c address h17, cpu address:h105 ? accessed by cpu, serial interface and i 2 c (r/w) in port based mode 75430 unitag port priority ultrust pvid bit[3:0]: ? pvid [11:8] (default is f) bit [4]: ? untrusted port. (default is 0) this register is used to change the vlan priori ty field of a packet to a predetermined priority. ? 1: vlan priority field is changed to bit[7:5] at ingress port ? 0: keep vlan priority field bit [7:5]: ? untag port priority (default 7) 765 3210 fp en drop default tx priority fnt if reserved bit [1:0]: reserved (default 0) bit [2]: force untagged out (default 0) ?0 disable ? 1 force untag output all packets transmitted from this port are untagged. this register is used when this port is connected to legacy equipment that does not support vlan tagging. bit [5:3]: fixed transmit priority. used when bit[7] = 1 (default 0) ? 000 transmit prio rity level 0 (lowest) ? 001 transmit priority level 1 ? 010 transmit priority level 2 ? 011 transmit priority level 3 ? 100 transmit priority level 4 ? 101 transmit priority level 5 ? 110 transmit priority level 6 ? 111 transmit priori ty level 7 (highest) bit [6]: fixed discard priority (default 0) ? 0 - discard priority level 0 (lowest) ? 1 - discard priority level 7(highest) bit [7]: enable fix priority (default 0) ? 0 disable fix priority. all frames are analyzed. transmit priority and drop priority are based on vlan ta g o r to s . ? 1 transmit priority and discard priority are based on values programmed in bit [6:3]
mvtx2804 data sheet 60 zarlink semiconductor inc. in tag based vlan mode 11.5 port vlan map pvmap00_0,1,3 i 2 c address h14,15,17; cpu address:h102,103,105) pvmap01_0,1,3 i 2 c address h18,19,1b; cpu address:h106,107,109) pvmap02_0,1,3 i 2 c address h1c,1d,1f; cpu address:h10a, 10b,10d) pvmap03_0,1,3 i 2 c address h20,21,23; cpu address:h10e, 10f,111) pvmap04_0,1,3 i 2 c address h24,25,27; cpu address:h112, 113,115) pvmap05_0,1,3 i 2 c address h28,29,2b; cpu address:h116, 117,119) pvmap06_0,1,3 i 2 c address h2c,2d,2f; cpu address:h11a, 11b,11d) pvmap07_0,1,3 i 2 c address h30,31,33; cpu address:h11e, 11f,121) bit [1]: ingress filter enable (default 1) ? 0 disable - ingress filter. packets with vlan not belonging to source port are forwarded if destination port belongs to the vlan. symmetric vlan. ? enable - packets are discarded when source port is not a vlan member. asymmetric vlan. bit [2]: force untagged out (default 1) . ? 0 disable ? 1 force untagged output. all packets transmitted from this port are untagged. this register is used when this port is connected to legacy equipment that does not support vlan tagging. bit [5:3]: fixed transmit priority (default 0) used when bit [7] = 1 ? 000 transmit prio rity level 0 (lowest) ? 001 transmit priority level 1 ? 010 transmit priority level 2 ? 011 transmit priority level 3 ? 100 transmit priority level 4 ? 101 transmit priority level 5 ? 110 transmit priority level 6 ? 111 transmit priori ty level 7 (highest) bit [6]: fixed discard priority (default 0) used when bit [7] = 1 ? 0 - discard priority level 0 (lowest) ? 1 discard priority level 1 (highest) bit [7]: enable fix priority (default 0) ? 0 disable fix priority. all frames are analyzed. transmit priority and drop priority are based on vlan ta g o r to s . ? 1 transmit priority and discard priority are based on values programmed in bit [6:3]
mvtx2804 data sheet 61 zarlink semiconductor inc. 11.5.1 pvmode ?i 2 c address: h038, cpu address:h126 ? accessed by cpu, serial interface (r/w) 11.6 group 2 address 11.6.1 port trunking group 11.6.1.1 trunk0 - trunk group 0 member (managed mode only) ? cpu address:h200 ? accessed by cpu, serial interface (r/w) ? bit [7:0] port7-0 bit map of trunk 0. (default 00) ? trunk0 provides a bitmap for trunk0 membership. example: to trunk ports 0 and 2 in trunk group 0, bits 0 and 2 of trunk0 must be set to 1. all others must be clear ed to ?0? to indicate that they are not members of the trunk 0. 11.6.1.2 trunk1 - trunk group 1 member (managed mode only) ? cpu address:h201 ? accessed by cpu, serial interface (r/w) ? bit [7:0] port7-0 bit map of trunk 1. (default 00) 11.6.1.3 trunk2- trunk group 2 member (managed mode only) ? cpu address:h202 ? accessed by cpu, serial interface (r/w) ? bit [7:0] port7-0 bit map of trunk 2. (default 00) 76543 10 ro mp bpdu dm reserved vmod bit [0]: ? vlan mode (vlan_enable) (default = 0) ? 1: tag based vlan mode ? 0: port based vlan mode bit [4]: ? disable mac address 0 ? 0: mac address 0 is not leaned. ? 1: mac address 0 is leaned. bit [5]: ? force bpdu as multicast frame (default 0) ?1: enable. ? 0: disable. bpdu packet is forwarded to cpu. bit [6]: ? mac/port ? 0: single mac address per system ? 1: single mac address per port bit [7]: ? routing option (force frame as switched frame) ? 1: routing frame to cpu is independent of ingress port spanning tree state ? 0: routing frame to cpu is dependent of ingress port spanning tree state
mvtx2804 data sheet 62 zarlink semiconductor inc. 11.6.1.4 trunk3- trunk group 3 member (managed mode only) ? cpu address:h203 ? accessed by cpu, serial interface (r/w) ? bit [7:0] port7-0 bit map of trunk 3. (default 00) 11.6.1.5 trunk_hash_mode - trunk hash mode ? cpu address:h206 ? accessed by cpu, serial interface (r/w) hash select. the hash selected is valid for trunk 0, 1, 2 and 3. 11.6.1.6 trunk0_mode - trunk group 0 mode (unmanaged mode) ?i 2 c address: h039, cpu address:h207 ? accessed by serial interface and i 2 c (r/w) port selection in unmanaged mode. trunk group 0 and trunk group 1 are enable accordingly to bits [1:0] when input pin p_d[9] = 0 (external pull down). trunk hash ? trunk group 0 achieve load balance by tr unk0_hash0 to 5. (only in managed mode) ? trunk group 1 achieve load balance by tr unk1_hash0 to 5. (only in managed mode) ? trunk group 2 achieve load balance by tr unk2_hash0 to 5. (only in managed mode) ? trunk group 3 achieve load balance by tr unk3_hash0 to 5. (only in managed mode) 7210 hash sel bit [1:0] ? (default 2'b00) ? 00 - use source and destination mac address for hashing. ? 01 - use source mac address for hashing. ? 10 - use destination mac address for hashing. ? 11 - not used. 7210 port sel bit [1:0] ? port member selection for trunk 0 and 1 in unmanaged mode (default 2'b00) ? 00 - only trunk group 0 is enable. port 0 and 1 are used for trunk group0 ? 01 - only trunk group 0 is enable. port 0,1 and 2 are used for trunk group0 ? 10 - only trunk group 0 is enable. port 0,1,2 and 3 are used for trunk group0 ? 11 - trunk group 0 and 1 are enable. port 0, 1 are used for trunk group0, and port 2 and 3 are used for trunk group1
mvtx2804 data sheet 63 zarlink semiconductor inc. 11.6.1.7 trunk0_hash0 - trunk group 0 hash result 0,1,2 destination port number ? cpu address:h208 ? accessed by cpu, serial interface (r/w) 11.6.1.8 trunk0_hash1 - trunk group 0 hash result 2,3,4,5 destination port number ? cpu address:h209 ? accessed by cpu, serial interface (r/w) 11.6.1.9 trunk0_hash2 - trunk group 0 hash result 5,6,7 destination port number ? cpu address:h20a ? accessed by cpu, serial interface (r/w) 11.6.1.10 trunk0_hash3 - trunk group 0 hash result 8,9,10 destination port number ? cpu address:h20b ? accessed by cpu, serial interface (r/w) 11.6.1.11 trunk0_hash4 - trunk group 0 hash result 10,11,12,13 destination port number ? cpu address:h20c ? accessed by cpu, serial interface (r/w) bit [2:0]: ? hash result 0 destination port number[2:0] (default 000) bit [5:3] ? hash result 1 destination port number[2:0] (default 001) bit [7:6] ? hash result 2 destination port number[1:0] (default 00) bit [0]: ? hash result 2 destination port number[2] (default 0) bit [3:1]: ? hash result 3 destination port number[2:0] (default 001) bit [6:4]: ? hash result 4 destination port number[2:0] (default 000) bit [7]: ? hash result 5 destination port number[0] (default 1) bit [1:0]: ? hash result 5 destination port number[2:1] (default 00) bit [4:2] ? hash result 6 destination port number[2:0] (default 000) bit [7:5] ? hash result 7 destination port number[2:0] (default 001) bit [2:0]: ? hash result 8 destination port number[2:0] (default 000) bit [5:3] ? hash result 9 destination port number[2:0] (default 001) bit [7:6] ? hash result 10 destination port number[1:0] (default 00) bit [0]: ? hash result 10 destination port number[2] (default 0) bit [3:1] ? hash result 11 destination port number[2:0] (default 001) bit[6:4] ? hash result 12 destination port number[2:0] (default (000) bit [7] ? hash result 13 destination port number[2:0] (default (1)
mvtx2804 data sheet 64 zarlink semiconductor inc. 11.6.1.12 trunk0_hash5 - trunk group 0 hash result 13,14,15 destination port number ? cpu address:h20d ? accessed by cpu, serial interface (r/w) 11.6.1.13 trunk1_mode - trunk group 1 mode (unmanaged mode) ?i 2 c address h03a; cpu address:20e ? accessed by cpu, serial interface and i 2 c (r/w) ? port selection in unmanaged mode. trunk group 2 and trunk group 3 are enable accordingly to bits [1:0] when input pin p_d[10] = 0. 11.6.1.14 trunk1_hash0 - trunk group 1 hash result 0, 1, 2 destination port number ? cpu address:h20f ? accessed by cpu, serial interface (r/w) 11.6.1.15 trunk1_hash1 - trunk group 1 has h result 2, 3, 4, 5 destination port number ? cpu address:h210 ? accessed by cpu, serial interface (r/w) bit [1:0]: hash result 13 destination port number[2:1] (default 00) bit [4:2] hash result 14 destination port number[2:0] (default 000) bit [7:5] hash result 15 destination port number[2:0] (default 001) 7210 port select bit [1:0]: ? port member selection for trunk 2 and 3 in unmanaged mode ? 00 - only trunk group 2 is enable. port 4 and 5 are used for trunk group 2 ? 01 - only trunk group 2 is enable. port 4, 5 and 6 are used for trunk group 2 ? 10 - only trunk group 2 is enable. port 4, 5, 6 and 7 are used for trunk group 2 ? 11 - trunk group 2 and trunk group 3 are enable. port 4 and 5 are used for trunk group 2, and port 6 and 7 are used for trunk group 3 bit [2:0]: ? hash result 0 destination port number[2:0] (default 000) bit [7:6] ? hash result 2 destination port number[1:0] (default 00) bit [5:3] ? hash result 1 destination port number[2:0] (default 001) bit [0]: ? hash result 2 destination port number[2] (default 0) bit [3:1 ? hash result 3 destination port number[2:0] (default 001) bit [6:4] ? hash result 4 destination port number[2:0] (default 000) bit [7] ? hash result 5 destination port number[0] (default 1)
mvtx2804 data sheet 65 zarlink semiconductor inc. 11.6.1.16 trunk1_hash2 - trunk group 1 hash result 5, 6, 7 destination port number ? cpu address:h211 ? accessed by cpu, serial interface (r/w) 11.6.1.17 trunk1_hash3 - trunk group 1 hash result 8, 9, 10 destination port number ? cpu address:h212 ? accessed by cpu, serial interface (r/w) 11.6.1.18 trunk1_hash4- trunk group 1 hash result 11, 12, 13 destination port number ? cpu address:h213 ? accessed by cpu, serial interface (r/w) 11.6.1.19 trunk1_hash5 - trunk group 1 hash result 13, 14, 15 destination port number ? cpu address:h214 ? accessed by cpu, serial interface (r/w) 11.6.1.20 trunk2_hash0 - trunk group 2 hash result 0, 1, 2 destination port number ? cpu address:h215 ? accessed by cpu, serial interface (r/w) bit [1:0]: ? hash result 5 destination port number[2:1] (default 00) bit [4:2] ? hash result 6 destination port number[2:0] (default 000) bit [7:5] ? hash result 7 destination port number[2:0] (default 001) bit [2:0] ? hash result 8 destination port number[2:0] (default 000) bit [5:3] ? hash result 9 destination port number[2:0] (default 001) bit [7:6] ? hash result 10 destination port number[1:0] (default 00) bit [0]: ? hash result 10 destination port number[2] (default 0) bit [3:1] ? hash result 11 destination port number[2:0] (default 001) bit [6:4] ? hash result 12 destination port number[2:0] (default (000) bit [7] ? hash result 13 destination port number[0] (default (1) bit [1:0]: ? hash result 13 destination port number[2:1] (default 00) bit [4:2] ? hash result 14 destination port number[2:0] (default 000) bit [7:5] ? hash result 15 destination port number[2:0] (default 001) bit [2:0]: ? hash result 0 destination port number[2:0] (default 100) bit [5:3] ? hash result 1 destination port number[2:0] (default 101) bit [7:6] ? hash result 2 destination port number[1:0] (default 00)
mvtx2804 data sheet 66 zarlink semiconductor inc. 11.6.1.21 trunk2_hash1 - trunk group 2 has h result 2, 3, 4, 5 destination port number ? cpu address:h216 ? accessed by cpu, serial interface (r/w) 11.6.1.22 trunk2_hash2 - trunk group 2 hash result 5, 6, 7 destination port number ? cpu address:h217 ? accessed by cpu, serial interface (r/w) 11.6.1.23 trunk2_hash3 - trunk group 2 hash result 8, 9, 10 destination port number ? cpu address:h218 ? accessed by cpu, serial interface (r/w) 11.6.1.24 trunk0_hash3 - trunk group 0 hash result 8,9,10 destination port number ? cpu address:h20b ? accessed by cpu, serial interface (r/w) 11.6.1.25 trunk0_hash4 - trunk group 0 hash result 10,11,12,13 destination port number ? cpu address:h20c ? accessed by cpu, serial interface (r/w) bit [0]: ? hash result 2 destination port number[2] (default 1) bit [3:1] ? hash result 3 destination port number[2:0] (default 101) bit [6:4] ? hash result 4 destination port number[2:0] (default 100) bit [7] ? hash result 5 destination port number[0] ( default 1) bit [1:0]: ? hash result 5 destination port number[2:1] (default 10) bit [4:2] ? hash result 6 destination port number[2:0] (default 100) bit [7:5] ? hash result 7 destination port number[2:0] (default 101) bit [2:0]: ? hash result 8 destination port number[2:0] (default 000) bit [5:3] ? hash result 9 destination port number[2:0] (default 001) bit [7:6] ? hash result 10 destination port number[1:0] (default 00) bit [2:0]: ? hash result 8 destination port number[2:0] (default 000) bit [5:3] ? hash result 9 destination port number[2:0] (default 001) bit [7:6] ? hash result 10 destination port number[1:0] (default 00) bit [0]: ? hash result 10 destination port number[2] (default 0) bit [3:1] ? hash result 11 destination port number[2:0] (default 001) bit[6:4] ? hash result 12 destination port number[2:0] (default (000) bit [7] ? hash result 13 destination port number[2:0] (default (1)
mvtx2804 data sheet 67 zarlink semiconductor inc. 11.6.1.26 trunk0_hash5 - trunk group 0 hash result 13,14,15 destination port number ? cpu address:h20d ? accessed by cpu, serial interface (r/w) 11.6.1.27 trunk1_mode - trunk group 1 mode (unmanaged mode) ?i 2 c address h03a; cpu address:20e ? accessed by cpu, serial interface and i 2 c (r/w) ? port selection in unmanaged mode. trunk group 2 and trunk group 3 are enable accordingly to bits [1:0] when input pin p_d[10] = 0. 11.6.1.28 trunk1_hash0 - trunk group 1 hash result 0, 1, 2 destination port number ? cpu address:h20f ? accessed by cpu, serial interface (r/w) 11.6.1.29 trunk1_hash1 - trunk group 1 has h result 2, 3, 4, 5 destination port number ? cpu address:h210 ? accessed by cpu, serial interface (r/w) bit [1:0]: hash result 13 destination port number[2:1] (default 00) bit [4:2] hash result 14 destination port number[2:0] (default 000) bit [7:5] hash result 15 destination port number[2:0] (default 001) 7210 port select bit [1:0]: ? port member selection for trunk 2 and 3 in unmanaged mode ? 00 - only trunk group 2 is enable. port 4 and 5 are used for trunk group 2 ? 01 - only trunk group 2 is enable. port 4, 5 and 6 are used for trunk group 2 ? 10 - only trunk group 2 is enable. port 4, 5, 6 and 7 are used for trunk group 2 ? 11 - trunk group 2 and trunk group 3 are enable. port 4 and 5 are used for trunk group 2, and port 6 and 7 are used for trunk group 3 bit [2:0]: ? hash result 0 destination port number[2:0] (default 000) bit [7:6] ? hash result 2 destination port number[1:0] (default 00) bit [5:3] ? hash result 1 destination port number[2:0] (default 001) bit [0]: ? hash result 2 destination port number[2] (default 0) bit [3:1 ? hash result 3 destination port number[2:0] (default 001) bit [6:4] ? hash result 4 destination port number[2:0] (default 000) bit [7] ? hash result 5 destination port number[0] (default 1)
mvtx2804 data sheet 68 zarlink semiconductor inc. 11.6.1.30 trunk1_hash2 - trunk group 1 hash result 5, 6, 7 destination port number ? cpu address:h211 ? accessed by cpu, serial interface (r/w) 11.6.1.31 trunk1_hash3 - trunk group 1 hash result 8, 9, 10 destination port number ? cpu address:h212 ? accessed by cpu, serial interface (r/w) 11.6.1.32 trunk1_hash4- trunk group 1 hash result 11, 12, 13 destination port number ? cpu address:h213 ? accessed by cpu, serial interface (r/w) 11.6.1.33 trunk1_hash5 - trunk group 1 hash result 13, 14, 15 destination port number ? cpu address:h214 ? accessed by cpu, serial interface (r/w) 11.6.1.34 trunk2_hash0 - trunk group 2 hash result 0, 1, 2 destination port number ? cpu address:h215 ? accessed by cpu, serial interface (r/w) bit [1:0]: ? hash result 5 destination port number[2:1] (default 00) bit [4:2] ? hash result 6 destination port number[2:0] (default 000) bit [7:5] ? hash result 7 destination port number[2:0] (default 001) bit [2:0] ? hash result 8 destination port number[2:0] (default 000) bit [5:3] ? hash result 9 destination port number[2:0] (default 001) bit [7:6] ? hash result 10 destination port number[1:0] (default 00) bit [0]: ? hash result 10 destination port number[2] (default 0) bit [3:1] ? hash result 11 destination port number[2:0] (default 001) bit [6:4] ? hash result 12 destination port number[2:0] (default (000) bit [7] ? hash result 13 destination port number[0] (default (1) bit [1:0]: ? hash result 13 destination port number[2:1] (default 00) bit [4:2] ? hash result 14 destination port number[2:0] (default 000) bit [7:5] ? hash result 15 destination port number[2:0] (default 001) bit [2:0]: ? hash result 0 destination port number[2:0] (default 100) bit [5:3] ? hash result 1 destination port number[2:0] (default 101) bit [7:6] ? hash result 2 destination port number[1:0] (default 00)
mvtx2804 data sheet 69 zarlink semiconductor inc. 11.6.1.35 trunk2_hash1 - trunk group 2 has h result 2, 3, 4, 5 destination port number ? cpu address:h216 ? accessed by cpu, serial interface (r/w) 11.6.1.36 trunk2_hash2 - trunk group 2 hash result 5, 6, 7 destination port number ? cpu address:h217 ? accessed by cpu, serial interface (r/w) 11.6.1.37 trunk2_hash3 - trunk group 2 hash result 8, 9, 10 destination port number ? cpu address:h218 ? accessed by cpu, serial interface (r/w) 11.6.1.38 trunk2_hash4 - trunk group 2 hash result 10, 11, 12, 13 destination port number ? cpu address:h219 ? accessed by cpu, serial interface (r/w) 11.6.1.39 trunk2_hash5 - trunk group 2 hash result 13, 14, 15 destination port number ? cpu address:h21a ? accessed by cpu, serial interface (r/w) bit [0]: ? hash result 2 destination port number[2] (default 1) bit [3:1] ? hash result 3 destination port number[2:0] (default 101) bit [6:4] ? hash result 4 destination port number[2:0] (default 100) bit [7] ? hash result 5 destination port number[0] ( default 1) bit [1:0]: ? hash result 5 destination port number[2:1] (default 10) bit [4:2] ? hash result 6 destination port number[2:0] (default 100) bit [7:5] ? hash result 7 destination port number[2:0] (default 101) bit [2:0]: ? hash result 8 destination port number[2:0] (default 000) bit [5:3] ? hash result 9 destination port number[2:0] (default 001) bit [7:6] ? hash result 10 destination port number[1:0] (default 00) bit [0]: ? hash result 10 destination port number[2] (default 1) bit [3:1] ? hash result 11 destination port number[2:0] (default 101) bit [6:4] ? hash result 12 destination port number[2:0] (default 1000) bit [7] ? hash result 13 destination port number[2:0] (default (1) bit [1:0]: ? hash result 13 destination port number[2:1] (default 10) bit [4:2] ? hash result 14 destination port number[2:0] (default 100) bit [7:5] ? hash result 15 destination port number[2:0] (default 101)
mvtx2804 data sheet 70 zarlink semiconductor inc. 11.6.1.40 trunk3_hash0 - trunk group 3 hash result 0, 1, 2 destination port number ? cpu address:h21b ? accessed by cpu, serial interface (r/w) 11.6.1.41 trunk3_hash1 - trunk group 3 has h result 2, 3, 4, 5 destination port number ? cpu address:h21c ? accessed by cpu, serial interface (r/w) 11.6.1.42 trunk3_hash2 - trunk group 3 hash result 5, 6, 7 destination port number ? cpu address:h21d ? accessed by cpu, serial interface (r/w) 11.6.1.43 trunk3_hash3 - trunk group 3 ha sh result 8, 9, 10 destination port number ? cpu address:h21e ? accessed by cpu, serial interface (r/w) 11.6.1.44 trunk3_hash4 - trunk group 3 hash result 10, 11, 12, 13 destination port number ? cpu address:h21f ? accessed by cpu, serial interface (r/w) bit [2:0]: ? hash result 0 destination port number[2:0] (default 100) bit [5:3] ? hash result 1 destination port number[2:0] (default 101) bit [7:6] ? hash result 2 destination port number[1:0] (default 00) bit [0]: ? hash result 2 destination port number[2] (default 1) bit [3:1] ? hash result 3 destination port number[2:0] (default 101) bit [6:4] ? hash result 4 destination port number[2:0] (default 100) bit [7] ? hash result 5 destination port number[0] (default 1) bit [1:0]: ? hash result 5 destination port number[2:1] (default 10) bit [4:2] ? hash result 6 destination port number[2:0] (default 100) bit [7:5] ? hash result 7 destination port number[2:0] (default 101) bit [2:0]: ? hash result 8 destination port number[2:0] (default 100) bit [5:3] ? hash result 9 destination port number[2:0] (default 101) bit [7:6] ? hash result 10 destination port number[1:0] (default 00) bit [0]: ? hash result 10 destination port number[2] (default 1) bit [3:1] ? hash result 11 destination port number[2:0] (default 101) bit [6:4] ? hash result 12 destination port number[2:0] (default (100) bit [7] ? hash result 13 destination port number[2:0] (default (1)
mvtx2804 data sheet 71 zarlink semiconductor inc. 11.6.1.45 trunk3_hash5 - trunk group 3 hash result 13, 14, 15 destination port number ? cpu address:h220 ? accessed by cpu, serial interface (r/w) 11.6.2 multicast hash registers multicast hash registers are used to distribute multicas t traffic. 16 + 2 registers are used to form a 16-entry array; each entry has 9 bits, with each bit represent ing one port. any port not belonging to a trunk group should be programmed with 1. ports belonging to the same trunk group should only have a single port set to ?1? per entry. the port set to ?1? is picked to transmi t the multicast frame when the hash value is met. 11.6.2.1 multicast_hash00 - multicast hash result0 mask byte [7:0] ? cpu address:h221 ? accessed by cpu, serial interface (r/w) ? bit [7:0] (default ff) 11.6.2.2 multicast_hash01 - multicast hash result1 mask byte [7:0] ? cpu address:h222 ? accessed by cpu, serial interface (r/w) ? bit [7:0] (default ff) 11.6.2.3 multicast_hash02 - multicast hash result2 mask byte [7:0] ? cpu address:h223 ? accessed by cpu, serial interface (r/w) ? bit [7:0] (default ff) bit [1:0]: ? hash result 13 destination port number[2:1] (default 10) bit [4:2] ? hash result 14 destination port number[2:0] (default 100) bit [7:5] ? hash result 15 destination port number[2:0] (default 101) bit 876543210 hash result = 0 hash result = 1 hash result = 2 ... hash result = 13 hash result = 14 hash result = 15 cpu port port 7 port 6 port 5 port 4 port 3 port 2 port 1 port 0
mvtx2804 data sheet 72 zarlink semiconductor inc. 11.6.2.4 multicast_hash03 - multicast hash result3 mask byte [7:0] ? cpu address:h224 ? accessed by cpu, serial interface (r/w) ? bit [7:0] (default ff) 11.6.2.5 multicast_hash04 - multicast hash result4 mask byte [7:0] ? cpu address:h225 ? accessed by cpu, serial interface (r/w) ? bit [7:0] (default ff) 11.6.2.6 multicast_hash05 - multicast hash result5 mask byte [7:0] ? cpu address:h226 ? accessed by cpu, serial interface (r/w) ? bit [7:0] (default ff) 11.6.2.7 multicast_hash06 - multicast hash result6 mask byte [7:0] ? cpu address:h227 ? accessed by cpu, serial interface (r/w) ? bit [7:0] (default ff) 11.6.2.8 multicast_hash07 - multicast hash result7 mask byte [7:0] ? cpu address:h228 ? accessed by cpu, serial interface (r/w) ? bit [7:0] (default ff) 11.6.2.9 multicast_hash08 - multicast hash result8 mask byte [7:0] ? cpu address:h229 ? accessed by cpu, serial interface (r/w) ? bit [7:0] (default ff) 11.6.2.10 multicast_hash09 - multicast hash result9 mask byte [7:0] ? cpu address:h22a ? accessed by cpu, serial interface (r/w) ? bit [7:0] (default ff) 11.6.2.11 multicast_hash10 - multicast hash result10 mask byte [7:0] ? cpu address:h22b ? accessed by cpu, serial interface (r/w) ? bit [7:0] (default ff)
mvtx2804 data sheet 73 zarlink semiconductor inc. 11.6.2.12 multicast_hash11 - multicast hash result11 mask byte [7:0] ? cpu address:h22c ? accessed by cpu, serial interface (r/w) ? bit [7:0] (default ff) 11.6.2.13 multicast_hash12 - multicast hash result12 mask byte [7:0] ? cpu address:h22d ? accessed by cpu, serial interface (r/w) ? bit [7:0] (default ff) 11.6.2.14 multicast_hash13 - multicast hash result13 mask byte [7:0] ? cpu address:h22e ? accessed by cpu, serial interface (r/w) ? bit [7:0] (default ff) 11.6.2.15 multicast_hash14 - multicast hash result14 mask byte [7:0] ? cpu address:h22f ? accessed by cpu, serial interface (r/w) ? bit [7:0] (default ff) 11.6.2.16 multicast_hash15 - multicast hash result15 mask byte [7:0] ? cpu address:h230 ? accessed by cpu, serial interface (r/w) ? bit [7:0] (default ff) 11.6.2.17 multicast_hashml - mu lticast hash bit[8] for result7-0 ? cpu address:h231 ? accessed by cpu, serial interface (r/w) ? bit [7:0] (default ff) 11.6.2.18 multicast_hashml - mu lticast hash bit[8] for result 15-8 ? cpu address:h232 ? accessed by cpu, serial interface (r/w) ? bit [7:0] (default ff) 11.7 group 3 address 11.7.1 cpu port configuration group mac5 to mac0 registers form the cpu address. when a packet with destination address equal to mac5[5:0] arrives, it is forwarded to the cpu. mac5 mac4 mac3 mac2 mac1 mac0 (mc bit)
mvtx2804 data sheet 74 zarlink semiconductor inc. 11.7.1.1 mac0 - cpu mac address byte 0 ? cpu address:h300 ? accessed by cpu ? bit [7:0] byte 0 of the cpu mac address. (default 8'00) 11.7.1.2 mac1 - cpu mac address byte 1 ? cpu address:h301 ? accessed by cpu ? bit [7:0] byte 1 of the cpu mac address. (default 8'00) 11.7.1.3 mac2 - cpu mac address byte 2 ? cpu address:h302 ? accessed by cpu ? bit [7:0] byte 2 of the cpu mac address. (default 8'00) 11.7.1.4 mac3 - cpu mac address byte 3 ? cpu address:h303 ? accessed by cpu ? bit [7:0] byte 3 of the cpu mac address. (default 8'00) 11.7.1.5 mac4 - cpu mac address byte 4 ? cpu address:h304 ? accessed by cpu ? bit [7:0] byte 4 of the cpu mac address. (default 8'00) 11.7.1.6 mac5 - cpu mac address byte 5 ? cpu address:h305 ? accessed by cpu ? bit [7:0] byte 5 of the cpu mac address. (default 8'00). these registers form the cpu mac address 11.7.1.7 int_mask0 - interrupt mask 0 ? cpu address:h306 ? accessed by cpu, serial interface (r/w) ? mask off the interrupt source the cpu can dynamically mask the interruption w hen it is busy and doesn't want to be interrupted bit [0]: ? cpu frame interrupt. cpu frame bu ffer has data for cpu to read (default 1'b1) bit [1]: ? control command frame 1 interrupt. control command frame buffer1 has data for cpu to read (default 1'b1) bit [2]: ? control command frame 2 interrupt. control command frame buffer2 has data for cpu to read (default 1'b1) bit [7:3]: ? reserved ? 1 - mask the interrupt ? 0 - unmask the interrupt (enable interrupt)
mvtx2804 data sheet 75 zarlink semiconductor inc. 11.7.1.8 int_mask1 - interrupt mask 1 ? cpu address:h307 ? accessed by cpu, serial interface (r/w) ? mark off the interrupt source 11.7.1.9 int_status0 - masked interrupt status register0 ? cpu address:h30a ? access by cpu, serial interface (ro) ? indicate the source of the masked interrupt. 11.7.1.10 int_status1 - masked interrupt status register1 ? (cpu address:h30b) ? access by cpu, serial interface (ro) ? indicate the source of the masked interrupt. bit [0]: ? from gigabit port 0 interrupt (default 1'b1) bit [1]: ? from gigabit port 1 interrupt (default 1'b1) bit [2]: ? from gigabit port 2 interrupt (default 1'b1) bit [3]: ? from gigabit port 3 interrupt (default 1'b1) bit [4]: ? from gigabit port 4 interrupt (default 1'b1) bit [5]: ? from gigabit port 5 interrupt (default 1'b1) bit [6]: ? from gigabit port 6 interrupt (default 1'b1) bit [7]: ? from gigabit port 7 interrupt (default 1'b1) ? 1 - mask the interrupt ? 0 - unmask the interrupt (enable interrupt) bit [0]: ? cpu frame interrupt. bit [1]: ? control command frame 1 interrupt. bit [2]: ? control command frame 2 interrupt. bit [3]: ? from any of the gigabit port interrupt. bit [7:4]: ? reserved. bit [0]: ? from gigabit port 0 interrupt bit [1]: ? from gigabit port 1 interrupt bit [2]: ? from gigabit port 2 interrupt bit [3]: ? from gigabit port 3 interrupt bit [4]: ? from gigabit port 4 interrupt bit [5]: ? from gigabit port 5 interrupt bit [6]: ? from gigabit port 6 interrupt bit [7]: ? from gigabit port 7 interrupt
mvtx2804 data sheet 76 zarlink semiconductor inc. 11.7.1.11 intp_mask0 - interrupt mask for mac port 0,1 ? cpu address:h30c ? accessed by cpu, serial interface (r/w) the cpu can dynamically mask the interruption w hen it is busy and doesn't want to be interrupted 1 - mask the interrupt 0 - unmask the interrupt (enable interrupt) bit[0]: port 0 statistic counter wrap around interrupt mask. an interrupt is generated when a statistic counter gets to its maximum value and wraps around. refer to hardware statistic counter for interrupt sources. (default 1'b1) bit [1]: port 0 link change mask. (default 1'b1) bit [4]: port 1 statistic counter wrap around interrupt mask. (default 1'b1) bit [5]: port 1 link change mask. (default 1'b1) 11.7.1.12 intp_mask1 - interrupt mask for mac port 2,3 ? cpu address:h30d ? accessed by cpu, serial interface (r/w) 11.7.1.13 intp_mask4 - interrupt mask for mac port 4,5 ? cpu address:h30e ? accessed by cpu, serial interface (r/w) 765 43 21 0 p1 p0 76543210 p3 p2 bit [0]: ? port 2 was mask (default 1'b1) bit [1]: ? port 2 link change mask (default 1'b1) bit [4]: ? port 3 was mask (default 1'b1) bit [5]: ? port 3 link change mask (default 1'b1) 76543210 p4 p5 bit [0]: ? port 4 was mask (default 1'b1) bit [1]: ? port 4 link change mask (default 1'b1) bit [4]: ? port 5 was mask (default 1'b1) bit [5]: ? port 5 link change mask (default 1'b1)
mvtx2804 data sheet 77 zarlink semiconductor inc. 11.7.1.14 intp_mask5 - interrupt mask for mac port 6,7 ? cpu address:h30f ? accessed by cpu, serial interface (r/w) 11.7.2 rqs - receive queue select ? cpu address:h310 ? accessed by cpu, serial interface (rw) ? this register selects which receive queue is enable to send data to the cpu. note : strip priority applies between different selected queues (q3>q2>q1>q0) when flush (drop frames) is enable, it starts when queu e is too long or entry is too old. a queue is too long when it reaches wred thresholds. queue 0 is not s ubject to early drop. packets in queue 0 are dropped only when the queue is too old. an entry is too old when it is older than the time programmed in the register tx_age [5:0]. cpu can dynamically program this register reading register rqss [7:4]. 11.7.3 rqss - receive queue status ? cpu address:h311 ? accessed by cpu, serial interface (ro) 765 43 21 0 p6 p7 bit [0]: ? port 6 was mask (default 1'b1) bit [1] ? port 6 link change mask (default 1'b1) bit [4] ? port 7 was mask (default 1'b1) bit [5]: ? port 7 link change mask (default 1'b1) 76543210 fq3 fq2 fq1 fq0 sq3 sq2 sq1 sq0 bit[0]: ? select queue 0. if set to one, this queue may be scheduled to cpu port. if set to zero, this queue will be blocked. if multiple queues are select ed, a strict priority will be applied. q3> q2> q1> q0. same applies to bits [3:1]. see qos application note for more information. bit[1]: ? select queue 1 bit[2]: ? select queue 2 bit[3]: ? select queue 3 bit[4]: ? enable flush queue 0 bit[5]: ? enable flush queue 1 bit[6]: ? enable flush queue 2 bit[7]: ? enable flush queue 3 76543210 lq3 lq2 lq1 lq0 neq3 neq2 neq1 neq0
mvtx2804 data sheet 78 zarlink semiconductor inc. cpu queue status: 11.7.4 tx_age - tx queue aging timer ?i 2 c address: h03b;cpu address:h312 ? accessed by cpu, serial interface (ro) 11.8 group 4 address 11.8.1 search engine group 11.8.1.1 agetime_low - mac address aging time low ?i 2 c address h03c; cpu address:h400 ? accessed by cpu, serial interface and i 2 c (r/w) ? bit [7:0] low byte of the mac address aging timer. (default 2c) ? the 2800 removes the mac address from the data base and sends a delete mac address control command to the cpu. mac address aging is enable/disable by boot strap t_d[9]. 11.8.1.2 agetime_high -mac address aging time high ?i 2 c address h03d; cpu address:h401 ? accessed by cpu, serial interface and i 2 c (r/w) ? bit [7:0]: high byte of the mac address aging timer. (default 00) ? aging time is based on the following equation: {agetime_high,agetime_low} x (# of mac entries x100sec) note : the number of entries= 66k when t_d[5] is pull down (sram memory size = 512k) and 34k when t_d[5] is pull up (sram memory size = 256k). 11.8.1.3 v_agetime - vlan to port aging time ? cpu address:h402 ? accessed by cpu (r/w) ? bit [7:0] - 2msec/unit. (default ff) bit[3:0]: ? queue 3 to 0 not empty bit[4]: ? head of line entry for queue 3 to 0 is valid for too long. cpu queue 0 has no wred threshold bit[7:5]: ? head of line entry for queue 3 to 0 is valid for too long or queue length is longer than wred threshold 7654 0 tx queue agent bit[4:0]: ? unit of 100ms (default 8)disable transmission queue aging if value is zero. bit[5] ? must be set to '0' bit[7:6]: ? reserved
mvtx2804 data sheet 79 zarlink semiconductor inc. 11.8.1.4 se_opmode - search engine operation mode ? cpu address:h403 ? accessed by cpu (r/w) 11.8.1.5 scan - scan control register ? cpu address:h404 ? accessed by cpu (r/w) 76543210 sl dms arp dra da drd drn fl bit [0]: ? 1 - enable fast learning mode. in this mode, the hardware learns all the new mac addresses at highest rate, and reports to the cpu while t he hardware scans the mac database. when the cpu report queue is full, the mac address is l earned and marked as ?not reported?. when the hardware scans the database and finds a mac addr ess marked as ?not reported? it tries to report it to the cpu. the scan rate must be set. scan control register sets the scan rate. (default 0) ? 0 - search engine learns a new mac address and sends a message to the cpu report queue. if queue is full, the learning is temporarily halted. bit [1]: ? 1 - disable report new vlan port association (default 0) ? 0 - report new vlan port association bit [2]: report control ? 1 - disable report mac address deletion (default 0) ? 0 - report mac address deletion (mac address is deleted from mct after aging time) bit [3]: delete control ? 1 - disable aging logic from removing mac during aging (default 0) ? 0 - mac address entry is removed when it is old enough to be aged. however, a report is still sent to the cpu in both cases, when bit[2] = 0 bit [4]: ? 1 - disable report aging vlan port association (default 0) ? 0 - enable report aging vlan. vlan is not re moved by hardware. the cpu needs to remove the vlan -port association. bit [5]: ? 1 - report arp packet to cpu (default 0) bit [6]: ? disable mct speedup aging (default 0) ? 1 - disable speedup aging when mct resource is low. ? 0 - enable speedup aging when mct resource is low. bit [7]: ? slow learning (default 0) ? 1- enable slow learning. learning is temporary disabled when search demand is high ? 0 - learning is performed independent of search demand 76 0 rratio
mvtx2804 data sheet 80 zarlink semiconductor inc. scan is used when fast learning is enabled (se_op mode bit 0). it is used for setting up the report rate for newly learned mac addresses to the cpu. examples: r= 0, ratio = 0: all aging rounds are used for aging r= 0, ratio = 1: aging and scanning in every other aging round r= 1, ratio = 7: in eight rounds, one is used for scanning and seven is used for aging r= 0, ratio = 7: in eight rounds, one is used for aging and seven is used for scanning 11.9 group 5 address 11.9.1 buffer control/qos group 11.9.1.1 fcbat - fcb aging timer ?i 2 c address h03e; cpu address:h500 11.9.1.2 qosc - qos control ?i 2 c address h03f; cpu address:h501 ? accessed by cpu, serial interface and i 2 c (r/w) bit [6:0]: ? ratio between database scanning and aging round (default 00) bit [7]: ? reverse the ratio between scanning round and aging round (default 0) 70 fcbat bit [7:0]: ? fcb aging time. unit of 1ms. (default ff) ? fcbat define the aging time out interval of fcb handle 76543 10 to s - d to s - p c p u q v f 1 c bit [0]: ? qos frame lost is ok. prio rity will be available for flow cont rol enabled source only when this bit is set (default 0) bit [4]: ? per vlan multicast flow control (default 0) ?0 - disable ?1 - enable bit [5]: ? cpu multicast queues size ? 0 = 16 entries ? 1 = 160 entries bit [6]: ? select tos bits for priority (default 0) ? 0 - use tos [4:2] bits to map the transmit priority ? 1 - use tos [5:3] bits to map the transmit priority
mvtx2804 data sheet 81 zarlink semiconductor inc. 11.9.1.3 fcr - flooding control register ?i 2 c address h040; cpu address:h502 ? accessed by cpu, serial interface and i 2 c (r/w) 11.9.1.4 avpml - vlan priority map ?i 2 c address h041; cpu address:h503 ? accessed by cpu, serial interface and i 2 c (r/w) registers avpml, avpmm, and avpmh allow the eight vlan priorities to map into eight internal level transmit priorities. under the internal transmit priority, ?seven? is the highest priority where as ?zero? is the lowest. this feature allows the user the flexibility of redefining the vlan priority field. for example, programming a value of 7 into bit 2:0 of the avpml register would map packet vlan priority) into internal transmit priority 7. the new priority is used only inside the 2804. when the packet goes out it carries the original priority. bit [7]: ? select tos bits for drop (default 0) ? 0 - use tos [4:2] bits to map the drop priority ? 1 - use tos [5:3] bits to map the drop priority 76543 0 tos timebase u2mr bit [3:0]: ? u2mr: unicast to multicast rate. units in terms of time base defined in bits [6:4]. this is used to limit the amount of flooding traffic. the value in u2mr specifies how many packets are allowed to flood within the time specified by bit [6:4]. to disable this function, program u2mr to 0. (default = 4'h8) bit [6:4]: ? timebase: (default = 000) ?000 = 10us ?001 = 20us ?010 = 40us ?011 = 80us ? 100 = 160us ? 01 = 320us ? 110 = 640us ? 111 = 10us , same as 000. bit [7]: ? select vlan tag or tos field (ip packets) to be preferentially picked to map transmit priority and drop priority (default = 0) . ? 0 - select vlan tag priority field over tos field ? 1 - select tos field over vlan tag priority field 765 32 0 vp2 vp1 vp0 bit [2:0]: ? mapped priority of 0 (default 000) bit [5:3]: ? mapped priority of 1 (default 001) bit [7:6]: ? mapped priority of 2 (default 10)
mvtx2804 data sheet 82 zarlink semiconductor inc. 11.9.1.5 avpmm - vlan priority map ?i 2 c address h042, cpu address:h504 ? accessed by cpu, serial interface and i 2 c (r/w) map vlan priority into eight level transmit priorities: 11.9.1.6 avpmh - vlan priority map ?i 2 c address h043, cpu address:h505 ? accessed by cpu, serial interface and i 2 c (r/w) map vlan priority into eight level transmit priorities: 11.9.1.7 tospml - tos priority map ?i 2 c address h044, cpu address:h506 ? accessed by cpu, serial interface and i 2 c (r/w) map tos field in ip packet into four level transmit priorities 11.9.1.8 tospmm - tos priority map ?i 2 c address h045, cpu address:h507 ? accessed by cpu, serial interface and i 2 c (r/w) 764310 vp5 vp4 vp3 vp2 bit [0]: ? mapped priority of 2 (default 0) bit [3:1]: ? mapped priority of 3 (default 011) bit [6:4]: ? mapped priority of 4 (default 100) bit [7]: ? mapped priority of 5 (default 1) 754 21 0 vp2 vp6 vp5 bit [1:0]: ? mapped priority of 5 (default 10) bit [4:2]: ? mapped priority of 6 (default 110) bit [7:5]: ? mapped priority of 7 (default 111) 765 32 0 tp2 tp1 tp0 bit [2:0]: ? mapped priority when tos is 0 (default 000) bit [5:3]: ? mapped priority when tos is 1 (default 001) bit [7:6] ? mapped priority when tos is 2 (default 10) 76 5 43 1 0 tp5 tp4 tp3 tp2
mvtx2804 data sheet 83 zarlink semiconductor inc. map tos field in ip packet into four level transmit priorities 11.9.1.9 tospmh - tos priority map ?i 2 c address h046, cpu address:h508 ? accessed by cpu, serial interface and i 2 c (r/w) map tos field in ip packet into four level transmit priorities: 11.9.1.10 avdm - vlan discard map ?i 2 c address h047, cpu address:h509 ? accessed by cpu, serial interface and i2 c (r/w) map vlan priority into frame discard when low priority buffer usage is above threshold. frames with high discard (drop) priority will be discarded (dropped) before frames with low drop priority. ? 0 - low discard priority ? 1 - high discard priority bit [0]: ? mapped priority when tos is 2 (default 0) bit [3:1]: ? mapped priority when tos is 3 (default 011) bit [6:4]: ? mapped priority when tos is 4 (default 100) bit [7]: ? mapped priority when tos is 5 (default 1) 754210 tp7 tp6 tp5 bit [1:0]: ? mapped priority when tos is 5 (default 01) bit [4:2]: ? mapped priority when tos is 6 (default 110) bit [7:5]: ? mapped priority when tos is 7 (default 111) 76543210 fdv7 fdv6 fdv5 fdv4 fdv3 fdv2 fdv1 fdv0 bit [0]: ? frame discard priority for frames with vlan transmit priority 0 (default 0) bit [1]: ? frame discard priority for fr ames with vlan transmit priority 1 (default 0) bit [2]: ? frame discard priority for frames with vlan transmit priority 2 (default 0) bit [3]: ? frame discard priority for fr ames with vlan transmit priority 3 (default 0) bit [4]: ? frame discard priority for fr ames with vlan transmit priority 4 (default 0) bit [5]: ? frame discard priority for fr ames with vlan transmit priority 5 (default 0) bit [6]: ? frame discard priority for fr ames with vlan transmit priority 6 (default 0) bit [7]: ? frame discard priority for frames with vlan transmit priority 7 (default 0)
mvtx2804 data sheet 84 zarlink semiconductor inc. 11.9.1.11 tosdml - tos discard map ?i 2 c address h048, cpu address:h50a ? accessed by cpu, serial interface and i 2 c (r/w) map tos into frame discard when low priority buffer usage is above threshold 11.9.2 bmrc - broadcast/multicast rate control ?i 2 c address h049, cpu address:h50b) ? accessed by cpu, serial interface and i 2 c (r/w) this broadcast and multicast rate defines for each port the number of incoming packet allowed to be forwarded within a specified time. once the packet rate is reac hed, packets will be dropped. to turn off the rate limit, program the field to 0. 11.9.3 ucc - unicast congestion control ?i 2 c address h04a, cpu address:h50c ? accessed by cpu, serial interface and i 2 c (r/w) 76543210 fdt7 fdt6 fdt5 fdt4 fdt3 fdt2 fdt1 fdt0 bit [0]: frame discard priority for frames with tos transmit priority 0 (default 0) bit [1]: frame discard priority for frames with tos transmit priority 1 (default 0) bit [2]: frame discard priority for frames with tos transmit priority 2 (default 0) bit [3]: frame discard priority for frames with tos transmit priority 3 (default 0) bit [4]: frame discard priority for frames with tos transmit priority 4 (default 0) bit [5]: frame discard priority for frames with tos transmit priority 5 (default 0) bit [6]: frame discard priority for frames with tos transmit priority 6 (default 0) bit [7]: frame discard priority for frames with tos transmit priority 7 (default 0) 7430 broadcast rate multicast rate bit [3:0]: multicast rate control number of multicast packets allowed within the time defined in bits 6 to 4 of the flooding control register (fcr). (default 0). bit [7:4]: broadcast rate control number of broadcast packets allowed within the time defined in bits 6 to 4 of the flooding control register (fcr). (default 0) 70 unicast congest threshold bit [7:0]: number of frame count. used for best effort dropping at b% when destination port's best effort queue reaches ucc threshold and shared pool is all in use. granularity 16 frame. (default: h07)
mvtx2804 data sheet 85 zarlink semiconductor inc. 11.9.4 mcc - multicast congestion control ?i 2 c address h0b7, cpu address:h50d ? accessed by cpu, serial interface and i 2 c (r/w) 11.9.5 prg - port reservation for giga ports ?i 2 c address h0b9, cpu address:h50f ? accessed by cpu, serial interface and i 2 c (r/w) 11.9.6 fcb reservation 11.9.6.1 sfcb - share fcb size ?i 2 c address h04e), cpu address:h510 ? accessed by cpu, serial interface and i 2 c (r/w) 70 fc reaction prd multicast congest threshold bit [3:0]: in multiples of two. used for triggering mc flow control when desti nation port's multicast best effort queue reaches mcc threshold. (default 5'h08) bit [4]: must be 0 bit [7:5]: flow control reaction period. ([7:5] *4 usec)+3 usec (default 3'h2). buffer low thd per source buffer reservation bit [3:0]: per source buffer reservation. define the space in the fdb reserved for each port. expressed in multiples of 16 packets. for each packet 1536 bytes are reserved in the memory. default: 4'ha for 4mb memory 4'h6 for 2mb memory 4'h3 for 1mb memory bits [7:4]: expressed in multiples of 16 packets. threshold for dropping all best effort frames when destination port best effort queues reach ucc thre shold and shared pool is all used and source port reservation is at or below the prg[7:4] le vel. also the threshold for initiating uc flow control. default: 4'h6 for 4mb memory 4'h2 for 2mb memory 4'h1 for 1mb memory shared buffer size 7 0 77 7 0
mvtx2804 data sheet 86 zarlink semiconductor inc. 11.9.6.2 c2rs - class 2 reserved size ?i 2 c address h04f, cpu address:h511 ? accessed by cpu, serial interface and i 2 c (r/w) 11.9.6.3 c3rs - class 3 reserved size ?i 2 c address h050, cpu address:h512 ? accessed by cpu, serial interface and i 2 c (r/w) 11.9.6.4 c4rs - class 4 reserved size ?i 2 c address h051, cpu address:h513 ? accessed by cpu, serial interface and i 2 c (r/w) 11.9.6.5 c5rs - class 5 reserved size ?i 2 c address h052; cpu address:h514 ? accessed by cpu, serial interface and i 2 c (r/w) bits [7:0]: ? expressed in multiples of 8. buffer reservation for shared pool. (default 4g & 4m = 8'd62) (default 4g & 2m = 8'd20) (default 4g & 1m = 8'd08 (default 8g & 4m = 8'd150) (default 8g & 2m = 8'd55) (default 8g & 1m = 8'd25 class 2 fcb reservation bits [7:0]: ? buffer reservation for class 2 (third lowest priority). granularity 2. (default 8'h00) class 3 fcb reservation bits [7:0]: ? buffer reservation for class 3. granularity 2. (default 8'h00) class 4 fcb reservation bits [7:0]: ? buffer reservation for class 4. granularity 2. (default 8'h00) class 5 fcb reservation bits [7:0]: ? buffer reservation for class 5. granularity 2. (default 8'h00) 7 0 7 0 7 0 7 0
mvtx2804 data sheet 87 zarlink semiconductor inc. 11.9.6.6 c6rs - class 6 reserved size ?i 2 c address h053; cpu address:h515 ? accessed by cpu, serial interface and i 2 c (r/w) 11.9.6.7 c7rs - class 7 reserved size ?i 2 c address h054; cpu address:h516 ? accessed by cpu, serial interface and i 2 c (r/w) 11.9.7 classes byte gigabit port 0 ? accessed by cpu; serial interface and i 2 c (r/w): 11.9.7.1 qosc00 - byte_c2_g0 ?i 2 c address h055, cpu address:h517 11.9.7.2 qosc01 - byte_c3_g0 ?i 2 c address h056, cpu address:h518 11.9.7.3 qosc02 - byte_c4_g0 ?i 2 c address h057, cpu address:h519 class 6 fcb reservation bits [7:0]: ? buffer reservation for class 6 (second highest priority). granularity 2. (default 8'h00) class 7 fcb reservation bits [7:0]: ? buffer reservation for class 7 (highest priority). granularity 2. (default 8'h00) bits [7:0]: ? byte count threshold for c2 queue wred (default 8'h28) ? (1024byte/unit when delay bound is used) ? (1024byte/unit when wfq is used) bits [7:0]: ? byte count threshold for c3 queue wred (default 8'h28) ? (512byte/unit when delay bound is used) ? (1024byte/unit when wfq is used) bits [7:0]: ? byte count threshold for c4 queue wred (default 8'h28) ? (256byte/unit when delay bound is used) ? (1024byte/unit when wfq is used) 7 0 7 0
mvtx2804 data sheet 88 zarlink semiconductor inc. 11.9.7.4 qosc03 - byte_c5_g0 ?i 2 c address h058, cpu address:h51a 11.9.7.5 qosc04 - byte_c6_g0 ?i 2 c address h059, cpu address:h51b 11.9.7.6 qosc05 - byte_c7_g0 ?i 2 c address h05a, cpu address:h51c qosc00 through qosc05 represent the values f-a in table 3 for gigabit port 0. they are per-queue byte thresholds for weighted random early drop (wred). qosc05 represents a, and qosc00 represents f. see qos application note for more information. 11.9.8 classes byte gigabit port 1 ? accessed by cpu; serial interface and i 2 c (r/w): 11.9.8.1 qosc06 - byte_c2_g1 ?i 2 c address h05b, cpu address:h51d 11.9.8.2 qosc07 - byte_c3_g1 ?i 2 c address h05c, cpu address:h51e 11.9.8.3 qosc08 - byte_c4_g1 ?i 2 c address h05d, cpu address:h51f bits [7:0]: ? byte count threshold for c5 queue wred (default 8'h28) ? (128byte/unit when delay bound is used) ? (1024byte/unit when wfq is used) bits [7:0]: ? byte count threshold for c6 queue wred (default 8'h50) ? (64byte/unit when delay bound is used) ? (1024byte/unit when wfq is used) bits [7:0]: ? byte count threshold for c6 queue wred (default 8'h50) ? (64byte/unit when delay bound is used) ? (1024byte/unit when wfq is used) bits [7:0]: ? byte count threshold for c2 queue wred (default 8'h28) ? (1024byte/unit when delay bound is used) ? (1024byte/unit when wfq is used) bits [7:0]: ? byte count threshold for c3 queue wred (default 8'h28) ? (512 byte/unit when delay bound is used) ? (1024 byte/unit when wfq is used) bits [7:0]: ? byte count threshold for c4 queue wred (default 8'h28) ? (256 byte/unit when delay bound is used) ? (1024byte/unit when wfq is used)
mvtx2804 data sheet 89 zarlink semiconductor inc. 11.9.8.4 qosc09 - byte_c5_g1 ?i 2 c address h05e, cpu address:h520 11.9.8.5 qosc0a - byte_c6_g1 ?i 2 c address h05f, cpu address:h521 11.9.8.6 qosc0b - byte_c7_g1 ?i 2 c address h060, cpu address:h522 qosc06 through qosc0b represent the values f-a in table 3. they are per-queue byte thresholds for random early drop. qosc0b represents a, and qosc06 represents f. see qos application note for more information 11.9.9 classes byte gigabit port 2 ? accessed by cpu; serial interface and i 2 c (r/w): 11.9.9.1 qosc0c - byte_c2_g2 ?i 2 c address h061, cpu address:h523 11.9.9.2 qosc0d - byte_c3_g2 ?i 2 c address h062, cpu address:h524 11.9.9.3 qosc0e - byte_c4_g2 ?i 2 c address h063, cpu address:h525 bits [7:0]: ? byte count threshold for c5 queue wred (default 8'h28) ? (128 byte/unit when delay bound is used) ? (1024 byte/unit when wfq is used) bits [7:0]: ? byte count threshold for c6 queue wred (default 8'h50) ? (64 byte/unit when delay bound is used) ? (1024 byte/unit when wfq is used) bits [7:0]: ? byte count threshold for c7 queue wred (default 8'h50) ? (64 byte/unit when delay bound is used) ? (1024 byte/unit when wfq is used) bits [7:0]: ? byte count threshold for c2 queue wred (default 8'h28) ? (1024 byte/unit when delay bound is used) ? (1024 byte/unit when wfq is used) bits [7:0]: ? byte count threshold for c3 queue wred (default 8'h28) ? (512 byte/unit when delay bound is used) ? (1024 byte/unit when wfq is used) bits [7:0]: ? byte count threshold for c4 queue wred (default 8'h28) ? (256 byte/unit when delay bound is used) ? (1024 byte/unit when wfq is used)
mvtx2804 data sheet 90 zarlink semiconductor inc. 11.9.9.4 qosc0f - byte_c5_g2 ?i 2 c address h064, cpu address:h526 11.9.9.5 qosc10 - byte_c6_g2 ?i 2 c address h065, cpu address:h527 11.9.9.6 qosc11 - byte_c7_g2 ?i 2 c address h066, cpu address:h528 qosc0c through qosc11 represent the values f-a in table 3. they are per-queue byte thresholds for random early drop. qosc11 represents a, and qosc0c represent s f. see qos application note for more information 11.9.10 classes byte gigabit port 3 ? accessed by cpu; serial interface and i2c (r/w): 11.9.10.1 qosc12 - byte_c2_g3 ?i 2 c address h067, cpu address:h529 11.9.10.2 qosc13 - byte_c3_g3 ?i 2 c address h068, cpu address:h52a 11.9.10.3 qosc14 - byte_c4_g3 ?i 2 c address h069, cpu address:h52b bits [7:0]: ? byte count threshold for c5 queue wred (default 8'h28) ? (128 byte/unit when delay bound is used) ? (1024 byte/unit when wfq is used) bits [7:0]: ? byte count threshold for c6 queue wred (default 8'h50) ? (64 byte/unit when delay bound is used) ? (1024 byte/unit when wfq is used) bits [7:0]: ? byte count threshold for c7 queue wred (default 8'h50) ? (64 byte/unit when delay bound is used) ? (1024 byte/unit when wfq is used) bits [7:0]: ? byte count threshold for c2 queue wred (default 8'h28) ? (1024 byte/unit when delay bound is used) ? (1024 byte/unit when wfq is used) bits [7:0]: ? byte count threshold for c3 queue wred (default 8'h28) ? (512 byte/unit when delay bound is used) ? (1024 byte/unit when wfq is used) bits [7:0]: ? byte count threshold for c4 queue wred (default 8'h28) ? (256 byte/unit when delay bound is used) ? (1024 byte/unit when wfq is used)
mvtx2804 data sheet 91 zarlink semiconductor inc. 11.9.10.4 qosc15 - byte_c5_g3 ?i 2 c address h06a, cpu address:h52c 11.9.10.5 qosc16 - byte_c6_g3 ?i 2 c address h06b, cpu address:h52d 11.9.10.6 qosc17 - byte_c7_g3 ?i 2 c address h06c, cpu address:h52e qosc12 through qosc17 represent the values f-a in ta ble 3. they are per-queue byte thresholds for random early drop. qosc17 represents a, and qosc12 represent s f. see qos application note for more information 11.9.11 classes byte gigabit port 4 ? accessed by cpu; serial interface and i 2 c (r/w): 11.9.11.1 qosc18 - byte_c2_g4 ?i 2 c address h06d, cpu address:h52f 11.9.11.2 qosc019 - byte_c3_g4 ?i 2 c address h06e, cpu address:h530 11.9.11.3 qosc1a - byte_c4_g4 ?i 2 c address h06f, cpu address:h531 bits [7:0]: ? byte count threshold for c5 queue wred (default 8'h28) ? (128 byte/unit when delay bound is used) ? (1024 byte/unit when wfq is used) bits [7:0]: ? byte count threshold for c6 queue wred (default 8'h50) ? (64 byte/unit when delay bound is used) ? (1024 byte/unit when wfq is used) bits [7:0]: ? byte count threshold for c7 queue wred (default 8'h50) ? (64 byte/unit when delay bound is used) ? (1024 byte/unit when wfq is used) bits [7:0]: ? byte count threshold for c2 queue wred (default 8'h28) ? (1024 byte/unit when delay bound is used) ? (1024 byte/unit when wfq is used) bits [7:0]: ? byte count threshold for c3 queue wred (default 8'h28) ? (512 byte/unit when delay bound is used) ? (1024 byte/unit when wfq is used) bits [7:0]: ? byte count threshold for c4 queue wred (default 8'h28) ? (256 byte/unit when delay bound is used) ? (1024 byte/unit when wfq is used)
mvtx2804 data sheet 92 zarlink semiconductor inc. 11.9.11.4 qosc1b - byte_c5_g4 ?i 2 c address h070, cpu address:h532 11.9.11.5 qosc1c - byte_c6_g4 ?i 2 c address h071, cpu address:h533 11.9.11.6 qosc1d- byte_c7_g4 ?i 2 c address h072, cpu address:h534 qosc18 through qosc1d represent the values f-a in t able 3. they are per-queue byte thresholds for random early drop. qosc1d represents a, and qosc18 represent s f. see qos application note for more information 11.9.12 classes byte gigabit port 5 ? accessed by cpu; serial interface and i 2 c (r/w): 11.9.12.1 qosc1e- byte_c2_g5 ?i 2 c address h073, cpu address:h535 11.9.12.2 qosc1f - byte_c3_g5 ?i 2 c address h074, cpu address:h536 11.9.12.3 qosc20 - byte_c4_g5 ?i 2 c address h075, cpu address:h537 bits [7:0]: ? byte count threshold for c5 queue wred (default 8'h28) ? (128 byte/unit when delay bound is used) ? (1024 byte/unit when wfq is used) bits [7:0]: ? byte count threshold for c6 queue wred (default 8'h28) ? (64 byte/unit when delay bound is used) ? (1024 byte/unit when wfq is used) bits [7:0]: ? byte count threshold for c7 queue wred (default 8'h28) ? (64 byte/unit when delay bound is used) ? (1024 byte/unit when wfq is used) bits [7:0]: ? byte count threshold for c2 queue wred (default 8'h28) ? (1024 byte/unit when delay bound is used) ? (1024 byte/unit when wfq is used) bits [7:0]: ? byte count threshold for c3 queue wred (default 8'h28) ? (512 byte/unit when delay bound is used) ? (1024 byte/unit when wfq is used) bits [7:0]: ? byte count threshold for c4 queue wred (default 8'h28) ? (256 byte/unit when delay bound is used) ? (1024 byte/unit when wfq is used)
mvtx2804 data sheet 93 zarlink semiconductor inc. 11.9.12.4 qosc21 - byte_c5_g5 ?i 2 c address h076, cpu address:h538 11.9.12.5 qosc22 - byte_c6_g5 ?i 2 c address h077, cpu address:h539 11.9.12.6 qosc23 - byte_c7_g5 ?i 2 c address h078, cpu address:h53a qosc1e through qosc23 represent the values f-a in t able 3. they are per-queue byte thresholds for random early drop. qosc23 represents a, and qosc1e represent s f. see qos application note for more information 11.9.13 classes byte gigabit port 6 ? accessed by cpu; serial interface and i2c (r/w): 11.9.13.1 qosc24 - byte_c2_g6 ?i 2 c address h079, cpu address:h53b 11.9.13.2 qosc25 - byte_c3_g6 ?i 2 c address h07a, cpu address:h53c 11.9.13.3 qosc26 - byte_c4_g6 ?i 2 c address h07b, cpu address:h53d bits [7:0]: ? byte count threshold for c5 queue wred (default 8'h28) ? (128 byte/unit when delay bound is used) ? (1024 byte/unit when wfq is used) bits [7:0]: ? byte count threshold for c6 queue wred (default 8'h50) ? (64 byte/unit when delay bound is used) ? (1024 byte/unit when wfq is used) bits [7:0]: ? byte count threshold for c4 queue wred (default 8'h50) ? (64 byte/unit when delay bound is used) ? (1024 byte/unit when wfq is used) bits [7:0]: ? byte count threshold for c2 queue wred (default 8'h28) ? (1024 byte/unit when delay bound is used) ? (1024 byte/unit when wfq is used) bits [7:0]: ? byte count threshold for c3 queue wred (default 8'h28) ? (512 byte/unit when delay bound is used) ? (1024 byte/unit when wfq is used) bits [7:0]: ? byte count threshold for c4 queue wred (default 8'h28) ? (256 byte/unit when delay bound is used) ? (1024 byte/unit when wfq is used)
mvtx2804 data sheet 94 zarlink semiconductor inc. 11.9.13.4 qosc27 - byte_c5_g6 ?i 2 c address h07c, cpu address:h53e 11.9.13.5 qosc28 - byte_c6_g6 ?i 2 c address h07d, cpu address:h53f 11.9.13.6 qosc29 - byte_c7_g6 ?i 2 c address h07e, cpu address:h540 qosc24 through qosc29 represent the values f-a in ta ble 3. they are per-queue byte thresholds for random early drop. qosc29 represents a, and qosc24 represent s f. see qos application note for more information. 11.9.14 classes byte gigabit port 7 ? accessed by cpu; serial interface and i 2 c (r/w): 11.9.14.1 qosc2a - byte_c2_g7 ?i 2 c address h07f, cpu address:h541 11.9.14.2 qosc2b - byte_c3_g7 ?i 2 c address h080, cpu address:h542 11.9.14.3 qosc2c - byte_c4_g7 ?i 2 c address h081, cpu address:h543 bits [7:0]: ? byte count threshold for c5 queue wred (default 8'h28) ? (128 byte/unit when delay bound is used) ? (1024 byte/unit when wfq is used) bits [7:0]: ? byte count threshold for c6 queue wred (default 8'h50) ? (64 byte/unit when delay bound is used) ? (1024 byte/unit when wfq is used) bits [7:0]: ? byte count threshold for c7 queue wred (default 8'h50) ? (64 byte/unit when delay bound is used) ? (1024 byte/unit when wfq is used) bits [7:0]: ? byte count threshold for c2 queue wred (default 8'h28) ? (1024 byte/unit when delay bound is used) ? (1024 byte/unit when wfq is used) bits [7:0]: ? byte count threshold for c3 queue wred (default 8'h28) ? (512 byte/unit when delay bound is used) ? (1024 byte/unit when wfq is used) bits [7:0]: ? byte count threshold for c4 queue wred (default 8'h28) ? (256 byte/unit when delay bound is used) ? (1024 byte/unit when wfq is used)
mvtx2804 data sheet 95 zarlink semiconductor inc. 11.9.14.4 1qosc2d - byte_c5_g7 ?i 2 c address h082, cpu address:h544 11.9.14.5 qosc2e - byte_c6_g7 ?i 2 c address h083, cpu address:h545 11.9.14.6 qosc2f - byte_c7_g7 ?i 2 c address h084, cpu address:h546 qosc00 through qosc05 represent the values f-a in ta ble 3. they are per-queue byte thresholds for random early drop. qosc05 represents a, and qosc00 represent s f. see qos application note for more information. 11.9.15 classes byte limit cpu ? accessed by cpu; serial interface and i 2 c (r/w): 11.9.15.1 qosc30 - byte_c01 ? cpu address:h547 11.9.15.2 qosc31 - byte_c02 ? cpu address:h548 11.9.15.3 qosc32 - byte_c03 ? cpu address:h549 qosc30 through qosc32 represent the values c-a for cpu port. the values a-c are per-queue byte thresholds for random early drop. qosc32 represent s a, and qosc30 represents c. queue 0 does not have weighted random drop. see qos application note for more information. bits [7:0]: ? byte count threshold for c5 queue wred (default 8'h28) ? (128 byte/unit when delay bound is used) ? (1024 byte/unit when wfq is used) bits [7:0]: ? byte count threshold for c6 queue wred (default 8'h50) ? (64 byte/unit when delay bound is used) ? (1024 byte/unit when wfq is used) bits [7:0]: ? byte count threshold for c5 queue wred (default 8'h50) ? (64 byte/unit when delay bound is used) ? (1024 byte/unit when wfq is used) bits [7:0]: ? byte count threshold for c1 queue (256byte/unit) bits [7:0]: ? byte count threshold for c2 queue (256byte/unit) bits [7:0]: ? byte count threshold for c3 queue (256byte/unit)
mvtx2804 data sheet 96 zarlink semiconductor inc. 11.9.16 classes wfq credit set 0 ? accessed by cpu only 11.9.16.1 qosc33 - credit_c0_g0 ? cpu address:h54a 11.9.16.2 qosc34 - credit_c1_g0 ? cpu address:h54b bits [5:0]: ? w0 - credit register for wfq. (default 6'h04) bits [7:6]: ? priority type. define one of the four qos mode of operation for port 0 (default 2'00) ? see table below: queue p7p6p5p4p3p2p1p0 option 1 bit [7:6] = 2'b00 delay bound be option 2 bit [7:6] = 2'b01 sp delay bound be option 3 bit [7:6] = 2'b10 sp wfq option 4 bit [7:6] = 2'b11 wfq credit for wfq - bit [5:0] w7w6w5w4w3w2w1w0 bits [7]: ? flow control allow during wfq scheme. (default 1'b1) ? 0 = not support qos when the source port flow control status is on. ? 1= always support qos) bits [6]: ? flow control be queue only. (default 1'b1) ? 0= do not send any frames if the xoff is on. ? 1= the p7-p2 frames can be sent even the xoff is on bits [5:0] ? w1 - credit register. (default 4'h04) fc_allow fc_be_only lost_ok egress- for dest fc_status ingress- for src fc status 0 0 0 go to be queue if (src fc or des fc on) otherwise normal 0 0 1 go to be queue if (dest fc on) otherwise normal 1 0 0 (wfq only) go to be queue if (src fc on) otherwise bad 101 (wfq only) always normal x 1 0 go to be queue if (src fc on) x 1 1 always normal
mvtx2804 data sheet 97 zarlink semiconductor inc. 11.9.16.3 qosc35 - credit_c2_g0 ? cpu address:h54c 11.9.16.4 qosc36 - credit_c3_g0 ? cpu address:h54d 11.9.16.5 qosc37 - credit_c4_g0 ? cpu address:h54e 11.9.16.6 qosc38 - credit_c5_g0 ? cpu address:h54f 11.9.16.7 qosc39- credit_c6_g0 ? cpu address:h550 11.9.16.8 qosc3a- credit_c7_g0 ? cpu address:h551 qosc33 through qosc3arepresents the set of wfq parame ters (see section 7.5) for gigabit port 0. the granularity of the numbers is 1, and their sum must be 64. qosc33 corresponds to w0, and qosc3a corresponds to w7. 11.9.17 classes wfq credit port g1 ? access by cpu only bits [5:0]: ? w2 - credit register. (default 4'h04) bits [7:6]: ? reserved bits [5:0]: ? w3 - credit register. (default 4'h04) bits [7:6]: ? reserved bits [5:0]: ? w4 - credit register. (default 4'h04) bits [7:6]: ? reserved bits [5:0]: ? w5 - credit register. (default 5'h8) bits [7:6]: ? reserved bits [5:0]: ? w6 - credit register. (default 5'h8) bits [7:6]: ? reserved bits [5:0]: ? w7 - credit register. (default 5'h10) bits [7:6]: ? reserved
mvtx2804 data sheet 98 zarlink semiconductor inc. 11.9.17.1 qosc3b - credit_c0_g1 ? cpu address:h552 11.9.17.2 qosc3c - credit_c1_g1 ? cpu address:h54b bits [5:0]: ? w0 - credit register for wfq. (default 6'h04) bits [7:6]: ? priority type. define one of the four qos mode of operation for port 1 (default 2'00) ? see table below: queue p7p6p5p4p3p2p1p0 option 1 bit [7:6] = 2'b00 delay bound be option 2 bit [7:6] = 2'b01 sp delay bound be option 3 bit [7:6] = 2'b10 sp wfq option 4 bit [7:6] = 2'b11 wfq credit for wfq - bit [5:0] w7 w6 w5 w4 w3 w2 w1 w0 bits [7]: ? flow control allow during wfq scheme. (default 1'b1) ? 0 = not support qos when the source port flow control status is on. ? 1= always support qos) bits [6]: ? flow control be queue only. (default 1'b1) ? 0= do not send any frames if the xoff is on. ? 1= the p7-p2 frames can be sent even the xoff is on bits [5:0] ? w1 - credit register. (default 4'h04) fc_allow fc_be_only lost_ok egress- for dest fc_status ingress- for src fc status 0 0 0 go to be queue if (src fc or des fc on) otherwise normal 0 0 1 go to be queue if (dest fc on) otherwise normal 1 0 0 (wfq only) go to be queue if (src fc on) otherwise bad 101(wfq only) always normal x 1 0 go to be queue if (src fc on) x 1 1 always normal
mvtx2804 data sheet 99 zarlink semiconductor inc. 11.9.17.3 qosc3d - credit_c2_g1 ? cpu address:h553 11.9.17.4 qosc3e - credit_c3_g1 ? cpu address:h554 11.9.17.5 qosc3f - credit_c4_g1 ? cpu address:h555 11.9.17.6 qosc40 - credit_c5_g1 ? cpu address:h556 11.9.17.7 qosc41- credit_c6_g1 ? cpu address:h557 11.9.17.8 qosc42- credit_c7_g1 ? cpu address:h558 qosc3b through qosc42 represents the set of wfq para meters (see section 7.5) for gigabit port 1. the granularity of the numbers is 1, and their sum mu st be 64. qosc3b corresponds to w0, and qosc42 corresponds to w7 bits [5:0]: ? w2 - credit register. (default 4'h04) bits [7:6]: ? reserved bits [5:0]: ? w3 - credit register. (default 4'h04) bits [7:6]: ? reserved bits [5:0]: ? w4 - credit register. (default 4'h04) bits [7:6]: ? reserved bits [5:0]: ? w5 - credit register. (default 5'h8) bits [7:6]: ? reserved bits [5:0]: ? w6 - credit register. (default 5'h8) bits [7:6]: ? reserved bits [5:0]: ? w7 - credit register. (default 5'h10) bits [7:6]: ? reserved
mvtx2804 data sheet 100 zarlink semiconductor inc. 11.9.18 classes wfq credit port g2 ? access by cpu only 11.9.18.1 qosc43 - credit_c0_g2 ? cpu address:h55a 11.9.18.2 qosc44 - credit_c1_g2 ? cpu address:h55b bits [5:0]: ? w0 - credit register for wfq. (default 6'h04) bits [7:6]: ? priority type. define one of the four qos mode of operation for port 2 (default 2'00) ? see table below: queue p7p6p5p4p3p2p1 option 1 bit [7:6] = 2'b00 delay bound be option 2 bit [7:6] = 2'b01 sp delay bound be option 3 bit [7:6] = 2'b10 sp wfq option 4 bit [7:6] = 2'b11 wfq credit for wfq - bit [5:0] w7w6w5w4w3w2w1w0 bits [7]: ? flow control allow during wfq scheme. (default 1'b1) ? 0 = not support qos when the source port flow control status is on. ? 1= always support qos) bits [6]: ? flow control be queue only. (default 1'b1) ? 0= do not send any frames if the xoff is on. ? 1= the p7-p2 frames can be sent even the xoff is on bits [5:0] ? w1 - credit register. (default 4'h04) fc_allow fc_be_only lost_ok egress- for dest fc_status ingress- for src fc status 0 0 0 go to be queue if (src fc or des fc on) otherwise normal 0 0 1 go to be queue if (dest fc on) otherwise normal 1 0 0 (wfq only) go to be queue if (src fc on) otherwise bad 1 0 1 (wfq only) always normal x 1 0 go to be queue if (src fc on) x 1 1 always normal
mvtx2804 data sheet 101 zarlink semiconductor inc. 11.9.18.3 qosc45 - credit_c2_g2 ? cpu address:h55c 11.9.18.4 qosc46 - credit_c3_g2 ? cpu address:h55d 11.9.18.5 qosc47 - credit_c4_g2 ? cpu address:h55e 11.9.18.6 qosc48 - credit_c5_g2 ? cpu address:h55f 11.9.18.7 qosc49- credit_c6_g2 ? cpu address:h560 11.9.18.8 qosc4a- credit_c7_g2 ? cpu address:h561 qosc43 through qosc4arepresents the set of wfq parame ters (see section 7.5) for gigabit port 2. the granularity of the numbers is 1, and their sum must be 64. qosc43 corresponds to w0, and qosc4a corresponds to w7. bits [5:0]: ? w2 - credit register. (default 4'h04) bits [7:6]: ? reserved bits [5:0]: ? w3 - credit register. (default 4'h04) bits [7:6]: ? reserved bits [5:0]: ? w4 - credit register. (default 4'h04) bits [7:6]: ? reserved bits [5:0]: ? w5 - credit register. (default 5'h8) bits [7:6]: ? reserved bits [5:0]: ? w6 - credit register. (default 5'h8) bits [7:6]: ? reserved bits [5:0]: ? w7 - credit register. (default 5'h10) bits [7:6]: ? reserved
mvtx2804 data sheet 102 zarlink semiconductor inc. 11.9.19 classes wfq credit port g3 ? access by cpu only 11.9.19.1 qosc4b - credit_c0_g3 ? cpu address:h562 11.9.19.2 qosc4 - credit_c1_g3 ? cpu address:h563 bits [5:0]: ? w0 - credit register for wfq. (default 6'h04) bits [7:6]: ? priority type. define one of the four qos mode of operation for port 3 (default 2'00) ? see table below: queue p7p6p5p4p3p2p1p0 option 1 bit [7:6] = 2'b00 delay bound be option 2 bit [7:6] = 2'b01 sp delay bound be option 3 bit [7:6] = 2'b10 sp wfq option 4 bit [7:6] = 2'b11 wfq credit for wfq - bit [5:0] w7w6w5w4w3w2w1w0 bits [7]: ? flow control allow during wfq scheme. (default 1'b1) ? 0 = not support qos when the source port flow control status is on. ? 1= always support qos) bits [6]: ? flow control be queue only. (default 1'b1) ? 0= do not send any fram es if the xoff is on. ? 1= the p7-p2 frames can be sent even the xoff is on bits [5:0] ? w1 - credit register. (default 4?h04) fc_allow fc_be_only lost_ok egress- for dest fc_status ingress- for src fc status 0 0 0 go to be queue if (src fc or des fc on) otherwise normal 0 0 1 go to be queue if (dest fc on) otherwise normal 1 0 0 (wfq only) go to be queue if (src fc on) otherwise bad 101(wfq only) always normal x 1 0 go to be queue if (src fc on) x 1 1 always normal
mvtx2804 data sheet 103 zarlink semiconductor inc. 11.9.19.3 qosc4d - credit_c2_g3 ? cpu address:h564 11.9.19.4 qosc4e - credit_c3_g3 ? cpu address:h565 11.9.19.5 qosc4f - credit_c4_g3 ? cpu address:h566 11.9.19.6 qosc50 - credit_c5_g3 ? cpu address:h567 11.9.19.7 qosc51- credit_c6_g3 ? cpu address:h568 11.9.19.8 qosc52- credit_c7_g3 ? cpu address:h569 qosc4b through qosc52 represents the set of wfq para meters (see section 7.5) for gigabit port 3. the granularity of the numbers is 1, and their sum mu st be 64. qosc4b corresponds to w0, and qosc52 corresponds to w7. bits [5:0]: ? w2 - credit register. (default 4'h04) bits [7:6]: ? reserved bits [5:0]: ? w3 - credit register. (default 4'h04) bits [7:6]: ? reserved bits [5:0]: ? w4 - credit register. (default 4'h04) bits [7:6]: ? reserved bits [5:0]: ? w5 - credit register. (default 5'h8) bits [7:6]: ? reserved bits [5:0]: ? w6 - credit register. (default 5'h8) bits [7:6]: ? reserved bits [5:0]: ? w7 - credit register. (default 5'h10) bits [7:6]: ? reserved
mvtx2804 data sheet 104 zarlink semiconductor inc. 11.9.20 classes wfq credit port g4 ? access by cpu only 11.9.20.1 qosc53 - credit_c0_g4 ? cpu address:h56a 11.9.20.2 qosc54 - credit_c1_g4 ? cpu address:h56b bits [5:0]: w0 - credit register for wfq. (default 6'h04) bits [7:6]: priority type. define one of the four qos mode of operation for port 4 (default 2'00) see table below: queue p7p6p5p4p3p2p1p0 option 1 bit [7:6] = 2'b00 delay bound be option 2 bit [7:6] = 2'b01 sp delay bound be option 3 bit [7:6] = 2'b10 sp wfq option 4 bit [7:6] = 2'b11 wfq credit for wfq - bit [5:0] w7 w6 w5 w4 w3 w2 w1 w0 bits [7]: ? flow control allow during wfq scheme. (default 1'b1) ? 0 = not support qos when the source port flow control status is on. ? 1= always support qos) bits [6]: ? flow control be queue only. (default 1'b1) ? 0= do not send any frames if the xoff is on. ? 1= the p7-p2 frames can be sent even the xoff is on bits [5:0] ? w1 -credit register. (default 4'h04) fc_allow fc_be_only lost_ok egress- for dest fc_status ingress- for src fc status 0 0 0 go to be queue if (src fc or des fc on) otherwise normal 0 0 1 go to be queue if (dest fc on) otherwise normal 1 0 0 (wfq only) go to be queue if (src fc on) otherwise bad 1 0 1 (wfq only) always normal x 1 0 go to be queue if (src fc on) x 1 1 always normal
mvtx2804 data sheet 105 zarlink semiconductor inc. 11.9.20.3 qosc55 - credit_c2_g4 ? cpu address:h56c 11.9.20.4 qosc56 - credit_c3_g4 ? cpu address:h56d 11.9.20.5 qosc57 - credit_c4_g4 ? cpu address:h56e 11.9.20.6 qosc58 - credit_c5_g4 ? cpu address:h56f 11.9.20.7 qosc59- credit_c6_g4 ? cpu address:h570 11.9.20.8 qosc5a- credit_c7_g4 ? cpu address:h571 qosc53 through qosc5a represents the set of wfq parameters (see section 7.5) for gigabit port 4. the granularity of the numbers is 1, and their sum must be 64. qosc53 corresponds to w0, and qosc5a corresponds to w7. bits [5:0]: ? w2 - credit register. (default 4'h04) bits [7:6]: ? reserved bits [5:0]: ? w3 - credit register. (default 4'h04) bits [7:6]: ? reserved bits [5:0]: ? w4 - credit register. (default 4'h04) bits [7:6]: ? reserved bits [5:0]: ? w5 - credit register. (default 5'h8) bits [7:6]: ? reserved bits [5:0]: ? w6 - credit register. (default 5'h8) bits [7:6]: ? reserved bits [5:0]: ? w7 - credit register. (default 5'h10) bits [7:6]: ? reserved
mvtx2804 data sheet 106 zarlink semiconductor inc. 11.9.20.9 classes wfq credit port g5 ? access by cpu only 11.9.20.10 qosc5b - credit_c0_g5 ? cpu address:h572 11.9.20.11 qosc5c - credit_c1_g5 ? cpu address:h573 bits [5:0]: ? w0 - credit register for wfq. (default 6'h04) bits [7:6]: ? priority type. define one of the four qos mode of operation for port 5 (default 2'00) ? see table below: queue p7p6p5p4p3p2p1p0 option 1 bit [7:6] = 2'b00 delay bound be option 2 bit [7:6] = 2'b01 sp delay bound be option 3 bit [7:6] = 2'b10 sp wfq option 4 bit [7:6] = 2'b11 wfq credit for wfq - bit [5:0] w7 w6 w5 w4 w3 w2 w1 w0 bits [7]: ? flow control allow during wfq scheme. (default 1'b1) ? 0 = not support qos when the source port flow control status is on. ? 1= always support qos) bits [6]: ? flow control be queue only. (default 1'b1) ? 0= do not send any frames if the xoff is on. ? 1= the p7-p2 frames can be sent even the xoff is on bits [5:0] ? w1 - credit register. (default 4'h04) fc_allow fc_be_only lost_ok egress- for dest fc_status ingress- for src fc status 0 0 0 go to be queue if (src fc or des fc on) otherwise normal 0 0 1 go to be queue if (dest fc on) otherwise normal 1 0 0 (wfq only) go to be queue if (src fc on) otherwise bad 1 0 1 (wfq only) always normal x 1 0 go to be queue if (src fc on) x 1 1 always normal
mvtx2804 data sheet 107 zarlink semiconductor inc. 11.9.20.12 qosc5d - credit_c2_g5 ? cpu address:h574 11.9.20.13 qosc5e - credit_c3_g5 ? cpu address:h575 11.9.20.14 qosc5f - credit_c4_g5 ? cpu address:h576 11.9.20.15 qosc60 - credit_c5_g5 ? cpu address:h577 11.9.20.16 qosc61- credit_c6_g5 ? cpu address:h578 11.9.20.17 qosc62- credit_c7_g5 ? cpu address:h579 qosc5b through qosc62 represents the set of wfq para meters (see section 7.5) for gigabit port 5. the granularity of the numbers is 1, and their sum mu st be 64. qosc5b corresponds to w0, and qosc62 corresponds to w7. bits [5:0]: ? w2 - credit register. (default 4'h04) bits [7:6]: ? reserved bits [5:0]: ? w3 - credit register. (default 4'h04) bits [7:6]: ? reserved bits [5:0]: ? w4 - credit register. (default 4'h04) bits [7:6]: ? reserved bits [5:0]: ? w5 - credit register. (default 5'h8) bits [7:6]: ? reserved bits [5:0]: ? w6 - credit register. (default 5'h8) bits [7:6]: ? reserved bits [5:0]: ? w7 - credit register. (default 5'h10) bits [7:6]: ? reserved
mvtx2804 data sheet 108 zarlink semiconductor inc. 11.9.21 classes wfq credit port g6 ? access by cpu only 11.9.21.1 qosc63 - credit_c0_g6 ? cpu address:h57a 11.9.21.2 qosc64 - credit_c1_g6 ? cpu address:h57b bits [5:0]: ? w0 - credit register for wfq. (default 6'h04) bits [7:6]: ? priority type. define one of the four qos mode of operation for port 6 (default 2'00) ? see table below: queue p7p6p5p4p3p2p1p0 option 1 bit [7:6] = 2'b00 delay bound be option 2 bit [7:6] = 2'b01 sp delay bound be option 3 bit [7:6] = 2'b10 sp wfq option 4 bit [7:6] = 2'b11 wfq credit for wfq - bit [5:0] w7 w6 w5 w4 w3 w2 w1 w0 bits [7]: ? flow control allow during wfq scheme. (default 1'b1) ? 0 = not support qos when the source port flow control status is on. ? 1= always support qos) bits [6]: ? flow control be queue only. (default 1'b1) ? 0= do not send any frames if the xoff is on. ? 1= the p7-p2 frames can be sent even the xoff is on bits [5:0] ? w1 - credit register. (default 4'h04) fc_allow fc_be_only lost_ok egress- for dest fc_status ingress- for src fc status 0 0 0 go to be queue if (src fc or des fc on) otherwise normal 0 0 1 go to be queue if (dest fc on) otherwise normal 1 0 0 (wfq only) go to be queue if (src fc on) otherwise bad 10 1(wfq only) always normal x 1 0 go to be queue if (src fc on) x 1 1 always normal
mvtx2804 data sheet 109 zarlink semiconductor inc. 11.9.21.3 qosc65 - credit_c2_g6 ? cpu address:h57c 11.9.21.4 qosc66 - credit_c3_g6 ? cpu address:h57d 11.9.21.5 qosc67 - credit_c4_g6 ? cpu address:h57e 11.9.21.6 qosc68 - credit_c5_g6 ? cpu address:h57f 11.9.21.7 qosc69- credit_c6_g6 ? cpu address:h580 11.9.21.8 qosc6a- credit_c7_g6 ? cpu address:h581 qosc63 through qosc6a represents the set of wfq parameters (see section 7.5) for gigabit port 6. the granularity of the numbers is 1, and their sum must be 64. qosc63 corresponds to w0, and qosc6a corresponds to w7. bits [5:0]: ? w2 - credit register. (default 4'h04) bits [7:6]: ? reserved bits [5:0]: ? w3 - credit register. (default 4'h04) bits [7:6]: ? reserved bits [5:0]: ? w4 - credit register. (default 4'h04) bits [7:6]: ? reserved bits [5:0]: ? w5 - credit register. (default 5'h8) bits [7:6]: ? reserved bits [5:0]: ? w6 - credit register. (default 5'h8) bits [7:6]: ? reserved bits [5:0]: ? w7 - credit register. (default 5'h10) bits [7:6]: ? reserved
mvtx2804 data sheet 110 zarlink semiconductor inc. 11.9.22 classes wfq credit port g7 ? access by cpu only 11.9.22.1 qosc6b - credit_c0_g7 ? cpu address:h582 11.9.22.2 qosc6c - credit_c1_g7 ? cpu address:h583 bits [5:0]: ? w0 - credit register for wfq. (default 6'h04) bits [7:6]: ? priority type. define one of the four qos mode of operation for port 7 (default 2'00) ? see table below: queue p7p6p5p4p3p2p1p0 option 1 bit [7:6] = 2'b00 delay bound be option 2 bit [7:6] = 2'b01 sp delay bound be option 3 bit [7:6] = 2'b10 sp wfq option 4 bit [7:6] = 2'b11 wfq credit for wfq - bit [5:0] w7w6w5w4w3w2w1w0 bits [7]: ? flow control allow during wfq scheme. (default 1'b1) ? 0 = not support qos when the source port flow control status is on. ? 1= always support qos) bits [6]: ? flow control be queue only. (default 1'b1) ? 0= do not send any fram es if the xoff is on. ? 1= the p7-p2 frames can be sent even the xoff is on bits [5:0] ? w1 - credit register. (default 4'h04) fc_allow fc_be_only lost_ok egress- for dest fc_status ingress- for src fc status 0 0 0 go to be queue if (src fc or des fc on) otherwise normal 0 0 1 go to be queue if (dest fc on) otherwise normal 1 0 0 (wfq only) go to be queue if (src fc on) otherwise bad 101 (wfq only) always normal x 1 0 go to be queue if (src fc on) x 1 1 always normal
mvtx2804 data sheet 111 zarlink semiconductor inc. 11.9.22.3 qosc6d - credit_c2_g7 ? cpu address:h584 11.9.22.4 qosc6e - credit_c3_g7 ? cpu address:h585 11.9.22.5 qosc6f - credit_c4_g7 ? cpu address:h586 11.9.22.6 qosc70 - credit_c5_g7 ? cpu address:h587 11.9.22.7 qosc71- credit_c6_g7 ? cpu address:h588 11.9.22.8 qosc72- credit_c7_g7 ? cpu address:h589 qosc6b through qosc72 represents the set of wfq para meters (see section 7.5) for gigabit port 7. the granularity of the numbers is 1, and their sum mu st be 64. qosc6b corresponds to w0, and qosc72 corresponds to w7. bits [5:0]: ? w2 - credit register. (default 4'h04) bits [7:6]: ? reserved bits [5:0]: ? w3 - credit register. (default 4'h04) bits [7:6]: ? reserved bits [5:0]: ? w4 - credit register. (default 4'h04) bits [7:6]: ? reserved bits [5:0]: ? w5 - credit register. (default 5'h8) bits [7:6]: ? reserved bits [5:0]: ? w6 - credit register. (default 5'h8) bits [7:6]: ? reserved bits [5:0]: ? w7 - credit register. (default 5'h10) bits [7:6]: ? reserved
mvtx2804 data sheet 112 zarlink semiconductor inc. 11.9.23 class 6 shaper control port g0 ? accessed by cpu only 11.9.23.1 qosc73 - token_rate_g0 ? cpu address:h58a 11.9.23.2 qosc74 - token_limit_g0 ? cpu address:h58b qosc73 and qosc74 correspond to parameters from sect ion 7.6 on the shaper for ef traffic. qosc73 is an integer less than 64 (average rate), with granularity 1. qosc74 is the programmed maximum value of the counter (maximum burst size). this value is expr essed in multiples of 16. qosc73 and qosc74 apply to gigabit port 0. register qosc39-credit_c6_g0 program s the peak rate. see qos application note for more information. 11.9.23.3 class 6 shaper control port g1 ? accessed by cpu only 11.9.23.4 qosc75 - token_rate_g1 ? cpu address:h58c 11.9.23.5 qosc76 - token_limit_g1 ? cpu address:h58d qosc75 and qosc76 correspond to parameters from sect ion 7.6 on the shaper for ef traffic. qosc75 is an integer less than 64 (average rate), with granularity 1. qosc76 is the programmed maximum value of the counter (maximum burst size). this value is expr essed in multiples of 16. qosc75 and qosc76 apply to gigabit port 0. register qosc41-credit_c6_g1 program s the peak rate. see qos application note for more information. bits [7:0]: ? bytes allow to transmit every frame time (0.512usec) when regulated by shaper logic. (default: 8'h08) bits [7:0]: ? bytes allow to continue transmit out when regulated by shaper logic. (16byte/unit) (default: 8'hc0) bits [7:0]: ? bytes allow to transmit every frame time (0.512usec) when regulated by shaper logic. (default: 8'h08) bits [7:0]: ? bytes allow to continue transmit out when regulated by shaper logic. (16byte/unit) (default: 8'hc0)
mvtx2804 data sheet 113 zarlink semiconductor inc. 11.9.24 class 6 shaper control port g2 ? accessed by cpu only 11.9.24.1 qosc77 - token_rate_g2 ? cpu address:h58e 11.9.24.2 qosc78 - token_limit_g2 ? cpu address:h58f qosc77 and qosc78 correspond to parameters from sect ion 7.6 on the shaper for ef traffic. qosc77 is an integer less than 64 (average rate), with granularity 1. qosc78 is the programmed maximum value of the counter (maximum burst size). this value is expr essed in multiples of 16. qosc77 and qosc78 apply to gigabit port 2. qosc49-credit_c6_g2 programs the peak rate. see qos application note for more information. 11.9.25 class 6 shaper control port g3 ? accessed by cpu only 11.9.25.1 qosc79 - token_rate_g3 ? cpu address:h590 11.9.25.2 qosc7a - token_limit_g3 ? cpu address:h591 qosc79 and qosc7a correspond to parameters from section 7.6 on the shaper for ef traffic. qosc79 is an integer less than 64 (average rate), with granularity 1. qosc7a is the programmed maximum value of the counter (maximum burst size). this value is expr essed in multiples of 16. qosc79 and qosc7a apply to gigabit port 3. qosc51-credit_c6_g3 programs the peak rate. see qos application note for more information. bits [7:0]: ? bytes allow to transmit every frame time (0.512usec) when regulated by shaper logic. (default: 8'h08) bits [7:0]: ? bytes allow to continue transmit out when regulated by shaper logic. (16byte/unit) (default: 8'hc0) bits [7:0]: ? bytes allow to transmit every fram e time (0.512usec) when regulated by shaper logic. (default: 8'h08) bits [7:0]: ? bytes allow to continue transmit out when regulated by shaper logic. (16byte/unit) (default: 8'hc0)
mvtx2804 data sheet 114 zarlink semiconductor inc. 11.9.26 class 6 shaper control port g4 ? accessed by cpu only 11.9.26.1 qosc7b - token_rate_g4 ? cpu address:h592 11.9.26.2 qosc7c - token_limit_g4 ? cpu address:h593 qosc7b and qosc7c correspond to parameters from sectio n 7.6 on the shaper for ef traffic. qosc7b is an integer less than 64, with granularity 1 (average rate). qosc7c is the programmed maximum value of the counter (maximum burst size). this value is express ed in multiples of 16. qosc7b and qosc7c apply to gigabit port 4. qosc59-credit_c6_g4 programs the peak rate. see qos application note for more information. 11.9.27 class 6 shaper control port g5 ? accessed by cpu only 11.9.27.1 qosc7d - token_rate_g5 ? cpu address:h594 11.9.27.2 qosc7e - token_limit_g5 ? cpu address:h595 qosc7d and qosc7e correspond to parameters from sect ion 7.6 on the shaper for ef traffic. qosc7d is an integer less than 64 (average rate), with granularity 1. qosc7e is the programmed maximum value of the counter c1 (maximum burst size). this value is expr essed in multiples of 16. qosc7d and qosc7e apply to gigabit port 5. qosc60-credit_c6_g5 programs the peak rate. see qos application note for more information. bits [7:0]: ? bytes allow to transmit every frame ti me (0.512usec) when regulated by shaper logic. (default: 8'h08) bits [7:0]: ? bytes allow to continue transmit out when regulated by shaper logic. (16byte/unit) (default: 8'hc0) bits [7:0]: ? bytes allow to transmit every fram e time (0.512usec) when regulated by shaper logic. (default: 8'h08) bits [7:0]: ? bytes allow to continue transmit out when regulated by shaper logic. (16byte/unit) (default: 8'hc0)
mvtx2804 data sheet 115 zarlink semiconductor inc. 11.9.28 class 6 shaper control port g6 11.9.28.1 accessed by cpu only 11.9.28.2 qosc7f - token_rate_g6 ? cpu address:h596 11.9.28.3 qosc80 - token_limit_g6 ? cpu address:h597 qosc7f and qosc80 correspond to parameters from section 7.6 on the shaper for ef traffic. qosc7f is an integer less than 64 (average rate), with granularity 1. qosc80 is the programmed maximum value of the counter c1 (maximum burst size). this value is expr essed in multiples of 16. qosc7f and qosc80 apply to gigabit port 6. qosc69-credit_c6_g6 programs the peak rate. see qos application note for more information. 11.9.29 class 6 shaper control port g7 ? accessed by cpu only 11.9.29.1 qosc81 - token_rate_g7 ? cpu address:h598 11.9.29.2 qosc82 - token_limit_g7 ? cpu address:h599 qosc81 and qosc82 correspond to parameters from sect ion 7.6 on the shaper for ef traffic. qosc81 is an integer less than 64 (average rate), with granularity 1. qosc82 is the programmed maximum value of the counter c1 (maximum burst size). this value is ex pressed in multiples of 16. qosc81 and qosc82 apply to gigabit port 7. qosc6f-credit_c6_g7 programs t he peak rate. see qos application note for more information. bits [7:0]: ? bytes allow to transmit every fram e time (0.512usec) when regulated by shaper logic. (default: 8'h08) bits [7:0]: ? bytes allow to continue transmit out when regulated by shaper logic. (16byte/unit) (default: 8'hc0) bits [7:0]: ? bytes allow to transmit every frame time (0.512usec) when regulated by shaper logic. (default: 8'h08) bits [7:0]: ? bytes allow to continue transmit ou t when regulated by shaper logic. (16byte/unit) (default: 8'hc0)
mvtx2804 data sheet 116 zarlink semiconductor inc. 11.9.30 rdrc0 - wred rate control 0 ?i 2 c address:h085, cpu address:h59a ? accessed by cpu, serial interface and i 2 c (r/w) 11.9.31 rdrc1 - wred rate control 1 ?i 2 c address:h086, cpu address:h59b ? accessed by cpu, serial interface and i 2 c (r/w) 11.10 group 6 address 11.10.1 misc group 11.10.1.1 mii_op0 - mii register option 0 ?i 2 c address:h0b1, cpu address:h600 ? accessed by cpu, serial interface and i 2 c (r/w) x rate y rate bits [7:4]: ? corresponds to the percentage x% in chapter 7. used for random early drop. granularity 6.25%. (default: 4'h8) bits[3:0]: ? corresponds to the percentage y% in chapter 7. used for random early drop. granularity 6.25%. (default: 4'he) z rate b rate bits [7:4]: ? corresponds to the percentage z% in chapter 7. used for random early drop. granularity 6.25%.%. (default: 4'h6) bits[3:0]: ? corresponds to the best effort frame dr op percentage b%, when shared pool is all in use and destination port best effort queue reaches ucc. used for random early drop. granularity 6.25%.%. (default: 4'h8) hfc 1prst np vendor spc. reg addr bit [7]: ? half duplex flow control (do not use half duplex mode) 0 = half duplex flow control always enable 1 = half duplex flow control by negotiation bit[6]: ? link partner reset auto-negotiate disable bit [5] ? next page enable 1: enable 0: disable bit[4:0]: ? vendor specified link status regi ster address (null va lue means don't use it) (default 00) 70 43 70 43 70 6 54
mvtx2804 data sheet 117 zarlink semiconductor inc. 11.10.1.2 mii_op1 - mii register option 1 ?i 2 c address:0b2, cpu address:h601 ? accessed by cpu, serial interface and i 2 c (r/w) 11.10.1.3 fen - feature register ?i 2 c address:h0b3, cpu address:h602 ? accessed by cpu, serial interface and i 2 c (r/w) speed bit location duplex bit location bits[3:0]: ? duplex bit location in vendor specified register bits [7:4]: ? speed bit location in vendor specified register (default 00) dml mii rp ip mul v-sp ds sc bits [0]: ? statistic counter enable (default 0) ?0 - disable ?1 - enable ? when statistic counter is enable, an interrupt control frame is generated to the cpu, every time a counter wraps around. this feature requires an external cpu. bits[1]: ? reserved bit [2]: ? support ds ef code. (default 0) ?0 - disable ? 1 - enable (all ports) ? when 101110 is detected in ds field (tos[7:2]), the frame priority is set for 110 and drop is set for 0. bit [3]: ? enable vlan spanning tree support (default 0) ?0 - disable ?1 - enable ? when vlan spanning tree is enable the register ecr1pn are not used to program the port spanning tree status. the port spanning tree status is programmed in the vlan status field. bit [4]: ? disable ip multicast support (default 1) ? 0 - enable ip multicast support ? 1 - disable ip multicast support ? when enable, igmp packets are identified by search engine and are passed to the cpu for processing. ip multicast packets are forwarded to the ip multicast group members according to the vlan port mapping table. bit [5]: ? enable report of new mac and vlan (default 0) ? 0 - disable report to cpu ? 1 - enable report to cpu ? when disable: new vlan port association r eport, new mac address report and aging report are disable for all ports. when enable, r egister se_opemode is used to enable/disable selectively each function. bit [6]: ? 0: enable mii management state machine (default 0) ? 1: disable mii management state machine 70 43 7 0 65 4 321
mvtx2804 data sheet 118 zarlink semiconductor inc. 11.10.1.4 miic0 - mii command register 0 ? cpu address:h603 ? accessed by cpu and serial interface only (r/w) ? bit [7:0] mii data [7:0] note : before programming mii command: set fen[6], check miic3, making sure no rdy, and no valid; then program mii command. 11.10.1.5 miic1 - mii command register 1 ? cpu address:h604 ? accessed by cpu and serial interface only (r/w) ? bit [7:0] mii data [15:8] note : before programming mii command: set fen[6], check miic3, making sure no rdy and no valid; then program mii command. 11.10.1.6 miic2 - mii command register 2 ? cpu address:h605 ? accessed by cpu and serial interface only (r/w) note: before programming mii command: set fen[6], check miic3, making sure no rdy and no valid; then program mii command. 11.10.1.7 miic3 - mii command register 3 ? cpu address:h606 ? accessed by cpu and serial interface only (r/w) note: before programming mii command: set fen[6], check miic3, making sure no rdy and no valid; then program mii command. bit [7]: ? 0: enable using mct link list structure ? 1: disable using mct link list structure mii op register address bits [4:0]: reg_ad - register phy address bit [6:5] op - operation code ?10? for read command and ?01? for write command rdy valid phy address bits [4:0]: phy_ad - 5 bit phy address bit [6] valid - data valid from phy (read only) bit [7] rdy - data is returned from phy (ready only) 7 0 654 70 654
mvtx2804 data sheet 119 zarlink semiconductor inc. 11.10.1.8 miid0 - mii data register 0 ? cpu address:h607 ? accessed by cpu and serial interface only (ro) ? bit [7:0] mii data [7:0] 11.10.1.9 miid1 - mii data register 0 ? cpu address:h608 ? accessed by cpu and serial interface only (ro) ? bit [7:0] mii data [15:8] 11.10.1.10 led mode - led control ?i 2 c address:h0b4; cpu address:h609 ? accessed by cpu, serial interface and i 2 c (r/w) lpbk out pattern clock rate hold time bit[1:0] ? sample hold time (default 2'b00) 2'b00- 8 msec 2'b01- 16 msec 2'b10- 32 msec 2'b11- 64 msec bit[3:2] ? led clock speed (serial mode) (default 2'b10) 2'b00- sclk/1282'b01- sclk/256 2'b10- sclk/10242'b11- sclk/2048 ? led clock speed (parallel mode) (default 2'b10) 2'b00- sclk/10242'b01- sclk/4096 2'b10- sclk/20482'b11- sclk/8192 70 65 43 21
mvtx2804 data sheet 120 zarlink semiconductor inc. bit[5:4] led indicator out pattern (default 2'b11) 2'b00- normal output, led signals go straight out, no logical combination 2'b01- 4 bi-color led mode 2'b10- 3 bi-color led mode 2'b11- programmable mode 1. normal mode: led_byteout_[7]:c ollision (col) led_byteout_[6]:full duplex (fdx) led_byteout_[5]:speed[1] (sp1) led_byteout_[4]:speed[0] (sp0) led_byteout_[3]:link (lnk) led_byteout_[2]:rx (rxd) led_byteout_[1]:tx (txd) led_byteout_[0]:flow control (fc) 2. 4 bi-color led mode led_byteout_[7]:col led_byteout_[6]:1000fdx led_byteout_[5]:1000hdx led_byteout_[4]:100fdx led_byteout_[3]:100hdx led_byteout_[2]:10fdx led_byteout_[1]:10hdx led_byteout_[0]:act note: all output qualified by link signal
mvtx2804 data sheet 121 zarlink semiconductor inc. 11.10.2 checksum - eeprom checksum ?i 2 c address h0c5, cpu address:h60b ? accessed by cpu, serial interface and i 2 c (r/w) 11.10.3 led user 11.10.3.1 leduser0 ?i 2 c address h0bb, cpu address:h60c ? accessed by cpu, serial interface and i 2 c (r/w) 3. 3 bi-color led mode: led_byteout_[7]:col led_byteout_[6]:lnk led_byteout_[5]:fc led_byteout_[4]:spd1000 led_byteout_[3]:spd100 led_byteout_[2]:fdx led_byteout_[1]:hdx led_byteout_[0]:act note: all output qualified by link signal 4. programmable mode: led_byteout_[7]:link led_byteout_[6:0]:defined by the ledsig6 ~ ledsig0 programmable registers. note: all output qualified by link signal bit[6]: ? reserved. must be '0' bit[7]: ? enable internal loop back. when this bit is se t to '1' all ports work in internal loop back mode. for normal operation must be '0'. bit[7:0]: (default 00) led user0 bit[7:0]: (default 00) content will send out by led serial logic 7 0
mvtx2804 data sheet 122 zarlink semiconductor inc. 11.10.3.2 leduser1 ?i 2 c address h0bc, cpu address:h60d ? accessed by cpu, serial interface and i 2 c (r/w) 11.10.3.3 leduser2/ledsig2 ?i 2 c address h0bd, cpu address:h60e ? accessed by cpu, serial interface and i 2 c (r/w) in serial mode: in parallel mode: this register is used for programming the led pin - led_byteout_[2] 11.10.3.4 leduser3/ledsig3 ?i 2 c address:h0be, cpu address:h60f ? access by cpu, serial interface (r/w) in serial mode: led user1 bit[7:0]: (default 00) content will send out by led serial logic led user2 bit[7:0]: (default 00) content will be sent out by led serial shift logic col fdx sp1 sp0 col fdx sp1 sp0 bit [3:0]: (default 4'h0) signal polarity: 0: not invert polarity (high true) 1: invert polarity bit [7:4] (default 4'h8) signal select: 0: not select 1: select the corresponding bit when bits get selected, the led_byteout_[2] = and (all selected bits) led user3 bit [7:0]: (default 8'h33) content will be sent out by led serial shift logic. 7 0 7 0 7 0 4 3 7 0
mvtx2804 data sheet 123 zarlink semiconductor inc. in parallel mode: this register is used for programming the led pin - led_byteout_[3] 11.10.3.5 leduser4/ledsig4 ?i 2 c address:h0bf, cpu address:h610 ? access by cpu, serial interface (r/w) in parallel mode: this register is used for programming the led pin - led_byteout_[4] 11.10.3.6 leduser5/ledsig5 ?i 2 c address:h0c0, cpu address:h611 ? access by cpu, serial interface (r/w) col fdx sp1 sp0 col fdx sp1 sp0 bit [3:0]: (default 4'h3) signal polarity: 0: not invert polarity (high true) 1: invert polarity bit [7:4] (default 4'h3) signal select: 0: not select 1: select the corresponding bit when bits get selected, the led_byteout_[3] = and (all selected bits) led user4 bit [7:0] (default 8'h32) content will be sent out by led serial shift logic. col fdx sp1 sp0 col fdx sp1 sp0 bit [3:0]: (default 4'h2) signal polarity: 0: not invert polarity (high true) 1: invert polarity bit [7:4] (default 4'h3) signal select: 0: not select 1: select the corresponding bit when bits get selected, the led_byt eout_[4] = and (all selected bits) led user5 bit [7:0] (default 8'h20) content will be sent out by led serial shift logic. 7 0 7 0 7 0 4 3 7 0
mvtx2804 data sheet 124 zarlink semiconductor inc. in parallel mode: this register is used for programming the led pin - led_byteout_[5] 11.10.3.7 leduser6/ledsig6 ?i 2 c address:h0c1, cpu address:h612 ? access by cpu, serial interface (r/w) in parallel mode: this register is used for programming the led pin - led_byteout_[6] col fdx sp1 sp0 col fdx sp1 sp0 bit [3:0] (default 4'h0) signal polarity: 0: not invert polarity (high true) 1: invert polarity bit [7:4] (default 4'h2) signal select: 0: not select 1: select the corresponding bit when bits get selected, the led_byteout_[5] = and (all selected bits) led user6 bit [7:0] (default 8'h40) content will be sent out by led serial shift logic. col fdx sp1 sp0 col fdx sp1 sp0 bit [3:0] (default 4'b0000) signal polarity: 0: not invert polarity (high true) 1: invert polarity bit [7:4] (default 4'b0100) signal select: 0: not select 1: select the corresponding bit when bits get selected, the led_byteout_[6] = and (all selected bits), or the polarity of led_byteout_[6] is controlled by ledsig1_0[3] 7 0 43 7 0 7 0 43
mvtx2804 data sheet 125 zarlink semiconductor inc. 11.10.3.8 leduser7/ledsig1_0 ?i 2 c address:h0c2, cpu address:h613 ? access by cpu, serial interface (r/w) in parallel mode: this register is used for programming the led pin - led_byteout_[2] 11.10.4 miinp0 - mii next page data register 0 ?i 2 c address:h0c3, cpu address:h614 ? access by cpu and serial interface only (r/w) 11.10.5 miinp1 - mii next page data register 1 ?i 2 c address:h0c4, cpu address:h615 access by cpu and serial interface only (r/w) led user7 bit [7:0] (default 8'h61) content will be sent out by led serial shift logic. gp rx tx fc p6 rx tx fc bit [7] (default 1'b0) global output polarity: this bit controls the output polarity of all led_byteout_ and led_port_sel pins. 0: no invert polarity - (led_by teout_[7:0] are high activated, led_port_sel[9:0] are low activated) 1: invert polarity - (led_byteout _[7:0] are low activated, led_por t_sel[9:0] are high activated) bit [6:4] (default 3'b110) signal select: 0: not select 1: select the corresponding bit when bits get selected, the led_byt eout_[6] = or (all selected bits) bit[3] (default 1'b0) polarity control of led_byteout_[6] 0: not invert 1: invert bit [2:0] (default 3'b001) signal select: 0: not select 1: select the corresponding bit when bits get selected, the led_byt eout_[0] = or (all selected bits) bit [7:0] mii next page data [7:0] bit [7:0] mii next page data [15:8] 7 0 7 0 43
mvtx2804 data sheet 126 zarlink semiconductor inc. 11.11 group f address 11.11.1 cpu access group 11.11.1.1 gcr-glob al control register ? cpu address: hf00 ? accessed by cpu and serial interface. (r/w) 11.11.1.2 dcr-device status and signature register ? cpu address: hf01 ? accessed by cpu and serial interface. (ro) init reset bist sr sc bit [0]: store configuration (default = 0) write '1' followed by '0' to store configuration into external eeprom bit[1]: store configuration and reset (default = 0) write '1' to store configuration into external eeprom and reset chip bit[2]: start bist (default = 0) write '1' followed by '0' to start the device's built-in self-test. the result is found in the dcr register. bit[3]: soft reset (default = 0) write '1' to reset the chip bit[4]: initialization done (default = 0) this bit is meaningless when cpu is not installed. in managed mode , cpu write this bit with ?1? to indicate initialization is comple ted and ready to forward packets. 1 - initialization is done 0 - initialization is not completed. bit[7] interrupt polarity (default = 0) 1 - interrupt active high 0 - interrupt active low revision signature re binp br bw bit [0]: 1 - busy writin g configuration to i 2 c 0 - not busy writing configuration to i 2 c bit[1]: 1 - busy reading configuration from i 2 c 0 - not busy reading configuration from i 2 c bit[2]: 1 - bist in progress 0 - bist not running bit[3]: 1 - ram error 0 - ram ok bit[5:4]: device signature 00 - 4 ports device, non-management mode 01 - 8 ports device, non-management mode 10 - 4 ports device, management mode possible (need to install cpu) 11 - 8 ports device, management mode possible (need to install cpu) 70 54 3 2 1 70 65 4 3 2 1
mvtx2804 data sheet 127 zarlink semiconductor inc. 11.11.1.3 dcr01-giga port status ? cpu address: hf02 ? accessed by cpu and serial interface. (ro) 11.11.1.4 dcr23-giga port status ? cpu address: hf03 ? accessed by cpu and serial interface. (ro) bit [7:6]: revision cic giga1 giga0 bit [1:0]: giga port 0 strap option - 00 - 100mb mii mode - 01 - 2g mode - 10 - gmii - 11 - pcs bit[3:2] giga port 1 strap option - 00 - 100mb mii mode - 01 - reserved - 10 - gmii - 11 - pcs bit [7] chip initialization completed. note : dcr01[7], dcr23[7], dcr45[7] and dcr67[7] have the same function. 7643210 cic giga3 giga2 bit [1:0]: giga port 2 strap option- 00 - 100mb mii mode - 00 - 100mb mii mode - 01 - reserved - 10 - gmii - 11 - pcs bit[3:2] giga port 3 strap option - 00 - 100mb mii mode - 01 - 2g mode - 10 - gmii - 11 - pcs bit [7] chip initialization completed 70 32 1 64
mvtx2804 data sheet 128 zarlink semiconductor inc. 11.11.1.5 dcr45-giga port status ? cpu address: hf04 ? accessed by cpu and serial interface. (ro) 11.11.1.6 dcr67-giga port status ? cpu address: hf05 ? accessed by cpu and serial interface. (ro) cic giga5 giga4 bit [1:0]: giga port 4 strap option - 00 - 100mb mii mode - 01 - reserved - 10 - gmii - 11 - pcs bit[3:2] giga port 5 strap option - 00 - 100mb mii mode - 01 - 2g mode - 10 - gmii - 11 - pcs bit [7] chip initialization completed cic giga7 giga6 bit [1:0]: giga port 6 strap option - 00 - 100mb mii mode - 01 - 2g mode - 10 - gmii - 11 - pcs bit[3:2] giga port 7 strap option - 00 - 100mb mii mode - 01 - reserved - 10 - gmii - 11 - pcs bit [7] chip initia lization completed 70 3 21 64 7 0 321 64
mvtx2804 data sheet 129 zarlink semiconductor inc. 11.11.1.7 dpst - device port status register ? cpu address:hf06 ? accessed by cpu and serial interface (r/w) 11.11.1.8 dtst - data read back register ? cpu address: hf07 ? accessed by cpu and serial interface (ro) this register provides various internal information as selected in dpst bit[2:0] bit[2:0]: read back index register. this is used for selecting what to read back from dtst. (default 00) - 3'b000 - port 0 operati ng mode and negotiation status - 3'b001 - port 1 operati ng mode and negotiation status - 3'b010 - port 2 operati ng mode and negotiation status - 3'b011 - port 3 operating mode and negotiation status - 3'b100 - port 4 operati ng mode and negotiation status - 3'b101 - port 5 operati ng mode and negotiation status - 3'b110 - port 6 operating mode and negotiation status - 3'b111 - port 7 operating mode and negotiation status 76 543210 md infodet sigdet giga lnkdn fe fdpx fc_en bit[0]: flow control enabled bit[1]: full duplex port bit[2]: fast ethernet port (if not giga) bit[3]: link is down bit[4]: giga port bit[5]: signal detect (when pcs interface mode) bit[6]: pipe signal detected (pipe mode only) bit[7]: module detected (for hot swap purpose)
mvtx2804 data sheet 130 zarlink semiconductor inc. 12.0 bga and ba ll signal description 12.1 bga views (top-view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 a avdd nc9 scan_ en lb_d[0] lb_d[4] lb_d[5] lb_d[10 ] lb_d[16 ] lb_d[19] lb_d[26 ] lb_d[31 ] lb_d[32 ] lb_d[36 ] lb_d[40 ] lb_d[45 ] s_clk lb_d[60 ] lb_a[3] lb_a[7] lb_a[11 ] lb_a[15 ] b_a[16] b_a[12] b_a[7] b_a[2] b_oe# b_d[27] b_d[26] nc4 nc3 b dev_cf [0] la_d[0] nc7 lb_d[1] lb_d[3] lb_d[6] lb_d[12 ] lb_d[17 ] lb_d[20] lb_d[28 ] lb_cs0 # lb_d[33 ] lb_d[37 ] lb_d[41 ] lb_d[47 ] lb_d[54 ] lb_d[58 ] lb_d[62 ] lb_a[6] lb_a[10 ] lb_a[13 ] b_a[17] b_a[13] b_a[8] b_a[3] b_we# b _d[30] dev_cf g[1] nc5 b_d[25] c la_d[1] la_clk la_d[3] nc6 lb_d[2] lb_d[8] lb_d[15 ] lb_d[18 ] lb_d[21] l_d[29] lb_rw# lb_d[34 ] lb_d[39 ] lb_d[43 ] lb_bd[4 8] lb_d[52 ] lb_d[57 ] lb_d[61 ] lb_a[4] lb_a[8] lb_a[12 ] b_a[18] b_a[14] b_a[11] b_a[5] b_a[4] b_d[28] avdd b_clk b_d[22] d la_d[2] la_d[5] la_d[9] nc8 lb_clk lb_d[9] lb_d[13 ] lb_d[23 ] lb_d[22] lb_d[24 ] lb_d[25 ] lb_d[35 ] lb_d[42 ] lb_d[44 ] lb_d[50 ] lb_d[51 ] lb_d[55 ] lb_d[63 ] lb_a[14 ] lb_a[18 ] lb_a[16 ] lb_a[19 ] b_a[9] b_a[10] b_adsc # nc2 b_d[29] b_d[24] b_d[18] b_d[21] e la_d[8] la_d[7] la_d[6] la_d[4] agnd lb_d[7] lb_d[14 ] lb_d[11 ] lb_d[27] lb_d[30 ] lb_cs1 # lb_d[38 ] lb_d[46 ] lb_d[49 ] lb_d[53 ] lb_d[56 ] lb_d[59 ] lb_a[5] lb_a[9] lb_a[17 ] lb_a[20 ] b_a[15] b_a[6] b_d[31] agnd b_d[17] b_d[23] b_d[19] b_d[16] b_d[14] f la_d[10 ] la_d[11 ] la_d[1 2] la_d[13] la_d[14 ] vss vss vdd vdd vcc vcc vcc vss vss vcc vcc vcc vdd vdd vss vss nc1 b_d[9] b_d[10] b_d[11] b_d[12] g la_d[15 ] la_d[16 ] la_d[1 9] la_d[18] la_d[17 ] vdd vdd b_d[20] b_d[4] b_d[3] b_d[6] b_d[7] h la_d[20 ] la_d[21 ] la_d[2 2] la_d[29] la_d[24 ] b_d[15] b_d[8] p_int# b_d[1] b_d[2] j la_d[23 ] la_d[25 ] la_d[2 6] la_d[27] la_d[31 ] vdd vdd b_d[13] p_a[1] p_a[2] p_we# p_rd# k la_d[28 ] la_d[30 ] la_cs0 # la_d[37] la_d[33 ] vdd vdd b_d[5] p_d[15] p_d[11] p_d[12] p_d[13] l la_cs1 # la_rw# la_d[3 2] la_d[46] la_d[41 ] p_cs# p_d[14] p_d[7] p_d[8] p_d[10] m la_d[34 ] la_d[35 ] la_d[3 6] la_d[53] la_d[48 ] vcc vcc p_a[0] b_d[0] p_d[3] p_d[4] p_d[5] n la_d[38 ] la_d[40 ] la_d[4 2] la_d[61] la_d[56 ] vcc vss vss vss vss vss vss vcc p_d[6] p_d[9] p_d[0] p_d[1] p_d[2] p la_d[43 ] la_d[44 ] la_d[4 5] la_a[4] la_d[39 ] vcc vss vss vss vss vss vss vcc t_d[15] t_d[11] t_d[12] t_d[13] t_d[14] r la_d[49 ] la_d[50 ] la_d[5 1] la_d[52] la_d[47 ] vss vss vss vss vss vss vss vss t_d[10] t_d[5] t_d[7] t_d[8] t_d[9] t la_d[58 ] la_d[57 ] la_d[5 5] la_d[54] la_a[7] vss vss vss vss vss vss vss vss t_d[6] t_d[4] t_d[2] t_d[1] t_d[0] u la_d[63 ] la_d[62 ] la_d[6 0] la_d[59] la_a[11 ] vcc vss vss vss vss vss vss vcc s_rst# t_d[3] tmode[ 1] tmode[ 0] resou t# v la_a[6] la_a[5] la_a[3] la_a[14] la_a[18 ] vcc vss vss vss vss vss vss vcc g7_rx d[7] g7_rx_ er lesyno # le_clk 0 le_do w la_a[10 ] la_a[9] la_a[8] la_a[20] g0_txd [1] vcc vcc g7_rx d[3] g7_rxd [1] g7_rx_ dv g7_rxd [6] g7_rxd [5] y la_a[15 ] la_a[13 ] la_a[12 ] g0_crs/ l g0_txd [4] g7_txd [6] g7_tx_ en g7_rxd [4] g7_rxd [2] g7_rxd [0] aa la_a[19 ] la_a[17 ] la_a[16 ] grefc[ 0] g0_txd [7] vdd vdd g7_txd [0] g7_txd [3] g7_col g7_rxc lk miitxck [7] ab miitxck [0] g0_txd [2] g0_tx d[0] g0_txc lk g0_tx_ er vdd vdd g6_rx d[7] g7_tx_ er g7_txd [7] g7_txd [5] g7_txd [4] ac g0_rxc lk g0_txd [5] g0_tx d[3] g0_rxd[ 2] g0_rxd [6] g6_rxd [2] g6_rxd [4] g7_txd [2] g7_txd [1] g7_crs /l ad g0_rxd [0] g0_tx_ en g0_co l g0_txd[ 6] g0_rx_ dv vss vdd g6_rx d[0] g6_rx_ er g7_txc lk grefc[ 7] g6_rx_ dv ae g0_rxd [5] g0_rxd [4] g0_rx d[3] g0_rxd[ 1] g1_txd [0] vss vdd vdd vdd vcc vcc vcc vss vss vcc vcc vcc vdd vdd vss vss g6_txd [7] g6_rxd [6] g6_rxd [5] g6_rxd [3] g6_rxd [1] af g0_rxd [7] g0_rx_ er grefc[ 1] g1_rxd[ 2] g1_rxd [5] g1_rxd [7] g2_txd [0] g2_txd [7] g2_rxd[2] g2_rxd [4] g2_rxd [5] g3_txd [1] g3_txd [6] g3_col g3_rxd [3] g3_rxd [6] ind_cm g3_rxd [4] g3_rx_ er g4_txd [3] g4_rxd [1] g4_rxd [4] g5_txd [2] g5_txd [4] g5_tx_ er g5_rxd [5] g6_rxc lk g6_txd [6] g6_col g6_tx_ er ag g1_txd [1] g1_txc lk g1crs/ l g1_txd[ 7] g2_txc lk g1_rxd [4] g2_txd [4] g2_txd [3] g2_rxd[3] g2_rxc lk g2_rxd [7] g2_rx_ er g3_tx_ en g3_rxd [0] g3_rxd [5] g3_rxd [7] grefc[ 4] m_mdio g4_txd [1] g4_rxd [5] g4_rxd [6] g4_rxd [7] g5_crs /l g5_txd [5] miitxck [5] g5_rxd [1] g6_txd [3] g6_txd [4] g6_tx_ en g6_txd [5] ah g1_txd [2] g1_txd [3] miitxc k[1] g1_rxd[ 0] g1_rxc lk g2crs/ l miitxck [2] g2_tx_ en g2_rxd[1] g2_rx_ dv g3_txc lk g3_txd [3] g3_txd [5] g3_rxc lk g3_rxd [2] g3_rx_ dv g4_txc lk g4_txd [4] g4_txd [6] g4_tx_ er g4_rxc lk g4_rx_ dv g4_rx_ er g5_txd [3] g5_tx_ en g5_rxd [3] g5_rxd [6] g6_txd [1] g6_txd [2] g6_txc lk aj g1_txd [5] g1_txd [4] g1_tx_ er g1_col g1_rxd [6] grefc[ 2] g2_txd [2] g2_txd [6] g2_rxd[0] g2_rxd [6] grefc[ 3] g3_txd [2] miitxck [3] g3_tx_ er g3_rxd [1] m_mdc g4_txd [0] g4_txd [5] g4_txd [7] g4_rxd [0] g4_col grefc[ 5] g5_txd [0] g5_txd [6] g5_rxd [0] g5_col g5_rxd [4] g5_rx_ er g6_crs /l g6_txd [0] ak g1_txd [6] g1_tx_ en g1_rx d[1] g1_rxd[ 3] g1_rx_ dv g1_rx_ er g2_txd [1] g2_txd [5] g2_tx_er g2_col g3_crs /l g3_txd [0] g3_txd [4] g3_txd [7] cm_clk g4crs/ l g4_txd [2] miitxck [4] g4_tx_ en g4_rxd [2] g4_rxd [3] g5_txc lk g5_txd [1] g5_txd [7] g5_rxd [2] g5_rxc lk g5_rxd [7] g5_rx_ dv miitxck [6] grefc[ 6] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
mvtx2804 data sheet 131 zarlink semiconductor inc. 12.2 ball-signal descriptions all pins are cmos type; all input pins are 5 volt tolerance, and all output pins are 3.3 cmos drive. 12.2.1 ball signal description in managed mode ball no(s) symbol i/o description cpu bus interface k27, l27, k30, k29, k28, l30, n27, l29, l28, n26, m30, m29, m28, n30, n29, n28 p_data[15:0] i/o-ts with pull up processor bus data bit [15:0] j28, j27, m26 p_a[2:0] input pro cessor bus address bit [2:0] j29 p_we# input with weak internal pull up cpu bus-write enable j30 p_rd# input with weak internal pull up cpu bus-read enable l26 p_cs# input with weak internal pull up chip select h28 p_int# output cpu interrupt frame buffer interface u1, u2, n4, u3, u4, t1, t2, n5, t3, t4, m4, r4, r3, r2, r1, m5, r5, l4, p3, p2, p1, n3, l5, n2, p5, n1, k4, m3, m2, m1, k5, l3, j5, k2, h4, k1, j4, j3, j2, h5, j1, h3, h2, h1, g3, g4, g5, g2, g1, f5, f4, f3, f2, f1, d3, e1, e2, e3, d2., e4, c3, d1, c1, b2 la_d[63:0] i/o-ts with pull up frame bank a- data bit [63:0] aa1, v5, aa2, aa3, y1, v4, y2, y3, u5, w1, w2, w3, t5, v1, v2, p4, v3 la_a[19:3] output frame bank a - address bit [19:3] w4 la_a[20] output with pull up frame bank a - address bit [20] c2 la_clk output frame bank a clock input k3 la_cs0# output with pull up frame bank a low portion chip selection l1 la_cs1# output with pull up frame bank a high portion chip selection l2 la_rw# output with pull up frame bank a read/write
mvtx2804 data sheet 132 zarlink semiconductor inc. d18, b18, c18, a17, e17, b17, c17, e16, d17, b16, e15, c16, d16, d15, e14, c15, b15, e13, a15, d14, c14, d13, b14, a14, c13, e12, b13, a13, d12, c12, b12, a12, a11, e10, c10, b10, e9, a10, d11, d10, d8, d9, c9, b9, a9, c8, b8, a8, c7, e7, d7, b7, e8, a7, d6, c6, e6, b6, a6, a5, b5, c5, b4,a4 lb_d[63:0] i/o-ts with pullup frame bank b- data bit [63:0] d22, d20, e20, d21, a21, d19, b21, c21, a20, b20, e19, c20, a19, b19, e18, c19, a18 lb_a[19:3] output frame bank b - address bit [19:3] e21 lb_a[20] output with pull up frame bank b - address bit [20] d5 lb_clk output frame bank b clock input b11 lb_cs0# output with pull up frame bank b low portion chip selection e11 lb_cs1# output with pull up frame bank b high portion chip selection c11 lb_rw# output with pull up frame bank b read/write switch database interface e24,b27, d27, c27, a27, a28, b30, d28, e27, c30, d30, g26, e28, d29, e26, e29, h26, e30, j26, f30, f29, f28, f27, h27, g30, g29, k26, g27, g28, h30, h29, m27 b_d[31:0] i/o-ts with pull up switch database domain - data bit [31:0] c22, b22, a22, e22, c23, b23, a23, c24, d24, d23, b24, a24, e23, c25, c26, b25, a25 b_a[18:2] output switch database address (512k) - address bit [18:2] c29 b_clk output switch database clock input d25 b_adsc# output with pull up switch database address status control b26 b_we# output with pull up switch database write chip select a26 b_oe# output with pull up switch database read chip select mii management interface aj16 m_mdc output mii management data clock - (common for all mii ports [7:0]) ball no(s) symbol i/o description cpu bus interface
mvtx2804 data sheet 133 zarlink semiconductor inc. ag18 m_mdio i/o-ts with pull up mii management data i/o - (common for all mii ports -[7:0])) 2.5mhz gmii / mii interface (193) gi gabit ethernet access port ad29, ak30, aj22, ag17, aj11, aj6, af3,aa4 gref_clk [7:0] input w/ pull up giga reference clock ak15 cm_clk input w/ pull up commo n clock shared by port g[7:0] af17 ind/cm input w/ pull up 1: se lect gref_clk[7:0] as clock 0: select cm_clk as clock for all ports aa30, ak29, ag25, ak18, aj13, ah7, ah3, ab1 mii tx clk[7:0] input w/ pull up input w/ pull up v26, w29, w30, y28, w26, y29, w27, y30, ab26, ae27, ae28, ac27, ae29, ac26, ae30, ad26 ak27, ah27, af26, aj27, ah26, ak25, ag26, aj25 ag22, ag21, ag20, af22, ak21, ak20, af21, aj20 ag16, af16, ag15, af18, af15, ah15, aj15, ag14 ag11, aj10, af11, af10, ag9, af9, ah9, aj9 af6, aj5, af5, ag6, ak4, af4, ak3, ah4 af1, ac5, ae1, ae2, ae3, ac4, ae4, ad1 g7_rxd[7:0] g6_rxd[7:0] g5_rxd[7:0] g4_rxd[7:0] g3_rxd[7:0] g2_rxd[7:0] g1_rxd[7:0] g0_rxd[7:0] input w/ pull up g[7:0] port - receive data bit [7:0] w28, ad30, ak28, ah22, ah16, ah10, ak5, ad5 g[7:0]_rx_dv input w/ pull down g[7:0]port - receive data valid v27, ad27, aj28, ah23, af19, ag12, ak6, af2 g[7:0]_rx_er input w/ pull up g[7:0]port - receive error ac30, aj29, ag23, ak16, ak11, ah6, ag3, y4 g[7:0]_crs/li nk input w/ pull down g[7:0]port - carrier sense ball no(s) symbol i/o description cpu bus interface
mvtx2804 data sheet 134 zarlink semiconductor inc. aa28, af29, aj26, aj21, af14, ak10, aj4, ad3 g[7:0]_col input w/ pull up g[7 :0]port - collision detected aa29, af27, ak26, ah21, ah14, ag10, ah5, ac1 g[7:0]_rxclk input w/ pull up g[7:0]port - receive clock ab28, y26, ab29, ab30, aa27, ac28, ac29, aa26 ae26, af28, ag30, ag28, ag27, ah29, ah28, aj30 ak24, aj24, ag24, af24, ah24, af23, ak23, aj23 aj19, ah19, aj18, ah18, af20, ak17, ag19, aj17 ak14, af13, ah13, ak13, ah12, aj12, af12, ak12 af8, aj8, ak8, ag7, ag8, aj7, ak7, af7 ag4, ak1, aj1, aj2, ah2, ah1, ag1, ae5 aa5, ad4, ac2, y5, ac3, ab2, w5, ab3 g7_txd[7:0] g6_txd[7:0] g5_txd[7:0] g4_txd[7:0] g3_txd[7:0] g2_txd[7:0] g1_txd[7:0] g0_txd[7:0] output g[7:0]port - transmit data bit [7:0] y27, ag29, ah25, ak19, ag13, ah8, ak2, ad2 g[7:0]_tx_en output w/ pull up g[7:0]port - transmit data enable ab27, af30, af25, ah20, aj14, ak9, aj3, ab5 g[7:0]_tx_er output w/ pull up g[7:0]port - transmit error ad28, ah30, ak22, ah17, ah11, ag5, ag2, ab4 g[7:0]_ txclk output g[7:0]port - gigabit transmit clock pma interface (193) gigabit ethernet access port (pcs) ad29, ak30, aj22, ag17, aj11, aj6, af3,aa4 gref_clk [7:0] input w/ pull up gigabit reference clock ak15 cm_clk input w/ pull up common clock shared by port g[7:0] af17 ind/cm input w/ pull up i: select gref_clk[7:0] as clock 0: select cm_clk as clock for all port ball no(s) symbol i/o description cpu bus interface
mvtx2804 data sheet 135 zarlink semiconductor inc. v26, w29, w30, y28, w26, y29, w27, y30 ab26, ae27, ae28, ac27, ae29, ac26, ae30, ad26 ak27, ah27, af26, aj27, ah26, ak25, ag26, aj25 ag22, ag21, ag20, af22, ak21, ak20, af21, aj20 ag16, af16, ag15, af18, af15, ah15, aj15, ag14 ag11, aj10, af11, af10, ag9, af9, ah9, aj9 af6, aj5, af5, ag6, ak4, af4, ak3, ah4 af1, ac5, ae1, ae2, ae3, ac4, ae4, ad1 g7_rxd[7:0] g6_rxd[7:0] g5_rxd[7:0] g4_rxd[7:0] g3_rxd[7:0] g2_rxd[7:0] g1_rxd[7:0] g0_rxd[7:0] input w/ pull up g[7:0]port - pma receive data bit [7:0] w28, ad30, ak28, ah22, ah16, ah10, ak5, ad5 gp[7:0]_rx_d [8] input w/ pull down g[7:0]port - pma receive data bit [8] v27, ad27, aj28, ah23, af19, ag12, ak6, af2 gp[7:0]_rx_d [9] input w/ pull up g[7:0]port - pma receive data bit [9] aa28, af29, aj26, aj21, af14, ak10, aj4, ad3 gp[7:0]_ rxclk 1 input w/ pull up g[7:0]port - pma receive clock 1 aa29, af27, ak26, ah21, ah14, ag10, ah5, ac1 gp[7:0]_rxcl k0 input w/ pull up g[7:0]port - pma receive clock 0 ball no(s) symbol i/o description cpu bus interface
mvtx2804 data sheet 136 zarlink semiconductor inc. ab28, y26, ab29, ab30, aa27, ac28, ac29, aa26 ae26, af28, ag30, ag28, ag27, ah29, ah28, aj30 ak24, aj24, ag24, af24, ah24, af23, ak23, aj23 aj19, ah19, aj18, ah18, af20, ak17, ag19, aj17 ak14, af13, ah13, ak13, ah12, aj12, af12, ak12 af8, aj8, ak8, ag7, ag8, aj7, ak7, af7 ag4, ak1, aj1, aj2, ah2, ah1, ag1, ae5 aa5, ad4, ac2, y5, ac3, ab2, w5, ab3 g7_txd[7:0] g6_txd[7:0] g5_txd[7:0] g4_txd[7:0] g3_txd[7:0] g2_txd[7:0] g1_txd[7:0] g0_txd[7:0] output g[7:0]port - pma transmit data bit [7:0] y27, ag29, ah25, ak19, ag13, ah8, ak2, ad2 gp[7:0]_txd[ 8] output w/ pull up g[7:0]port - pma transmit data bit [8] ab27, af30, af25, ah20, aj14, ak9, aj3, ab5 gp[7:0]_txd[ 9] output w/ pull up g[7:0]port - pma transmit data bit [9] ad28, ah30, ak22, ah17, ah11, ag5, ag2, ab4 g[7:0]_ txclk output g[7:0]port - pma gigabit transmit clock test facility (3) u29 t_mode0 i/o-ts with pull up test - set upon reset, and provides nand tree test output during test mode use external pull up for normal operation u28 t_mode1 i/o-ts with pull up test - set upon reset, and provides nand tree test output during test mode use external pull up for normal operation a3 scan_en input w/ pull down enable test mode for normal operation leave it open ball no(s) symbol i/o description cpu bus interface
mvtx2804 data sheet 137 zarlink semiconductor inc. led interface (serial and parallel) r28, t26, r27, t27, u27, t28, t29, t30 t_d[7:0]/ led_pd[7:0] output while resetting, t_d[7,0] are in input mode and are used as strapping pins. internal pullup led_pd - parallel led data [7:0] p26, p30, p29, p28, p27, r26, r30, r29 t_d[15:8]/ led_pt[7:0] output while resetting, t_d[15:8] are in input mode and are used as strapping pins. internal pullup led_pr[7:0] - parallel led port sel [7:0] v29 led_clk0/ led_pt[8] output led_clk0 - led serial interface output clock led_pt[8] - parallel led port sel [8] v30 led_blink/ led_do/ led_pt[9] output while resetting, led-blink is in input mode and is used as strapping pin. 1: no blink, 0: blin k. internal pullup. led_do - led serial data output stream led_pt[9] - parallel led port sel [9] v28 led_pm/ led_synco# output w/ pull up while resett ing, led_pm is in input mode and is used as strapping pin. internal pull up. 1: enable parallel interface, 0: enable serial interface. led_synco# - led output data stream envelop system clock, power, and ground pins a16 s_clk input system clock at 133 mhz u26 s_rst# input - st reset input u30 resout# output reset phy b1 dev_cfg[0] input w/ pull down not used b28 dev_cfg[1]i input w/ pull down not used ae7, ae9, f10, f21, f22, f9, g25, g6, j25, j6, k25, k6, aa25, aa6, ab25, ab6, ad25, ae10, ae21, ae22 vdd power core +2.5 volt dc supply ball no(s) symbol i/o description cpu bus interface
mvtx2804 data sheet 138 zarlink semiconductor inc. v14, v15, v16, v17, v18, f16, f24, f25, f6, f7, n13, n14, n15, n16, n17, n18, p13, p14, p15, p16, p17, p18, r13, r14, r15, r16, r17, r18, r25, r6, t13, t14, t15, t16, t17, t18, t25, t6, u13, u14, u15, u16, u17, u18, v13, ad6, ae15, ae16, ae24, ae25, ae6, f15 vss ground ground a1, c28 avdd power analog +2.5 volt dc supply e5, e25 avss ground analog ground ae12, ae13, ae14, ae17, ae18, ae19, f12, f13, f14, f17, f18, f19, m25, m6, n25, n6, p25, p6, u25, u6, v25, v6, w25, w6 vcc power i/o +3.3 volt dc supply bootstrap pins (default= pull up, 1= pull up 0= pull down) ad2,ab5 g0_tx_en g0_tx_er default: pcs giga0 mode: g0_txen g0_txer 0 0 mii 0 1 rsvd 1 0 gmii 1 1 pcs ak2,aj3 g1_tx_en g1_txer default: pcs giga1 mode: g1_txen g1_txer 0 0 mii 0 1 rsvd 1 0 gmii 1 1 pcs ah8,ak9 g2_tx_en g2_tx_er default: pcs giga2 mode: g2_txen g2_txer 0 0 mii 0 1 rsvd 1 0 gmii 1 1 pcs ag13,aj14 g3_tx_en g3_tx_er default: pcs giga3 mode: g3_txen g3_txer 0 0 mii 0 1 rsvd 1 0 gmii 1 1 pcs ball no(s) symbol i/o description cpu bus interface
mvtx2804 data sheet 139 zarlink semiconductor inc. ak19,ah20 g4_tx_en g4_tx_er default: pcs giga4 mode: g4_txen g4_txer 0 0 mii 0 1 rsvd 1 0 gmii 1 1 pcs ah25,af25 g5_tx_en g5_tx_er default: pcs giga5 mode: g5_txen g5_txer 0 0 mii 0 1 rsvd 1 0 gmii 1 1 pcs ag29,af30 g6_tx_en g6_tx_er default: pcs giga6 mode: g6_txen g6_txer 0 0 mii 0 1 rsvd 1 0 gmii 1 1 pcs y27,ab27 g7_tx_en g7_tx_er default: pcs giga7 mode: g7_txen g7_txer 0 0 mii 0 1 rsvd 1 0 gmii 1 1 pcs after reset t_d[15:0] are used by the led interface t30 t_d[0] 1 giga link active status 0 - active low 1 - active high t29 t_d[1] 1 power saving 0 - no power saving 1 - power saving stop mac clock if no mac activity. t28 t_d[2] must be pulled-down reserved - must be pulled-down u27 t_d[3] 1 hot plug port module detection enable 0 - module detection enable 1 - module detection disable t27 t_d[4] must be pulled-down reserved - must be pulled-down r27 t_d[5] 1 sram memory size 0 - 512k sram 1 - 256k sram t26 t_d[6] 1 cpu port mode 0 ? 8 bit cpu data bus 1 ? 16 bit cpu data bus r28 t_d[7] 1 fdb memory depth 1- one memory layer 0 - two memory layers ball no(s) symbol i/o description cpu bus interface
mvtx2804 data sheet 140 zarlink semiconductor inc. w4, e21 la_a[20], lb_a[20] 1 fdb memory size 11 - 2m per bank = 4m total 10 - 1m per bank = 2m total 0x - 512k per bank = 1m total r29 t_d[8] 1 eeprom installed 0 - eeprom is installed 1 - eeprom is not installed r30 t_d[9] 1 mct aging enable 0 - mct aging disable 1 - mct aging enable r26 t_d[10] 1 fcb handle aging enable 0 - fcb handle aging disable 1 - fcb handle aging enable p27 t_d[11] 1 timeout reset enable 0 - timeout reset disable 1 - timeout reset enable issue reset if any state machine did not go back to idle for 5sec. p28, p29 t_d[13:12] 1 reserved p30 t_d[14] 1 cpu installed 0 - cpu installed 1 - cpu is not installed p26 t_d[15] 1 external ram test 0 - perform the infinite loop of zbt ram bist. debug test only 1 - regular operation. after reset p_d[8:0] are used by the cpu bus interface n30, n29, n28 p_d[2:0] 111 zbt ram la_clk turning 3'b000 - control by reg. lclkcr[2:0] 3'b001 - delay by method # 0 3'b010 - delay by method # 1 3'b011 - delay by method # 2 3'b100 - delay by method # 3 3'b101 - delay by method # 4 3'b110 - delay by method # 5 3'b111 - delay by method # 6 use method 6 for normal operation. external pull up not required ball no(s) symbol i/o description cpu bus interface
mvtx2804 data sheet 141 zarlink semiconductor inc. notes # = active low signal input = input signal in-st = input signal with schmitt-trigger output = output signal (tri-state driver) out-od= output signal with open-drain driver i/o-ts = input & output signal with tri-state driver i/o-od = input & output signal with open-drain driver m30, m29, m28 p_d[5:3] 111 zbt ram lb_clk turning 3'b000 - control by reg. lclkcr[6:4] 3'b001 - delay by method # 0 3'b010 - delay by method # 1 3'b011 - delay by method # 2 3'b100 - delay by method # 3 3'b101 - delay by method # 4 3'b110 - delay by method # 5 3'b111 - delay by method # 6 use method 6 for normal operation. external pull up not required l29, l28, n26 p_d[8:6] 111 sbram b_clk turning 3'b000 - control by bclkcr[2:0] 3'b001 - delay by method # 0 3'b010 - delay by method # 1 3'b011 - delay by method # 2 3'b100 - delay by method # 3 3'b101 - delay by method # 4 3'b110 - delay by method # 5 3'b111 - delay by method # 6 use method 6 for normal operation. external pull up not required ball no(s) symbol i/o description cpu bus interface
mvtx2804 data sheet 142 zarlink semiconductor inc. 12.2.2 ball - signal description in unmanaged mode ball no(s) symbol i/o description k27, l27, k30, k29, k28 p_data[15:11] i/o-ts with pull up not used - leave unconnected l30 p_data[10] i/o - ts with pull up trunk enable in unmanaged mode external pull up or unconnected - disable trunk group 0 and 1 external pull down - enable trunk group 0 and 1 see register trunk0_mode for port selection and trunk enable. n27 p_data[9] i/o - ts with pull up trunk enable in unmanaged mode external pull up or unconnected - disable trunk group 2 and 3 external pull down - enable trunk group 2 and 3 see register trunk1_mode for port selection and trunk enable l29, l28, n26, m30, m29, m28, n30, n29, n28 p_data[8:0] i/o - ts with pull up bootstrap function - see bootstrap section j28 p_a[2] input not used - leave unconnected h28 p_int# output with internal weak pullup not used - leave unconnected i 2 c interface (0) note: in unmanaged mode, use i 2 c and serial control interface to configure the system j27 scl output i 2 c data clock m26 sda i/o-ts with pull up i 2 c data i/o serial control interface j29 ps_strobe input wit h weak internal pull up serial strobe pin j30 ps_di input with weak internal pull up serial data input l26 ps_do (autofd) output with pull up serial data output (autofd) frame buffer interface u1, u2, n4, u3, u4,t1,t2, n5, t3, t4, m4, r4, r3, r2, r1, m5, r5, l4, p3, p2, p1, n3,l5, n2, p5, n1, k4, m3, m2, m1, k5, l3, j5, k2, h4, k1, j4, j3, j2, h5, j1, h3, h2, h1, g3, g4, g5, g2, g1, f5, f4, f3, f2, f1, d3, e1,e2,e3, d2., e4, c3, d1, c1, b2 la_d[63:0] i/o-ts with pull up fr ame bank a- data bit [63:0] aa1, v5, aa2, aa3, y1, v4, y2, y3, u5, w1, w2, w3, t5, v1, v2, p4, v3 la_a[19:3] output frame bank a - address bit [19:3]
mvtx2804 data sheet 143 zarlink semiconductor inc. w4 la_a[20] output with pull up frame bank a - address bit [20] c2 la_clk output frame bank a clock input k3 la_cs0# output with pull up frame bank a low portion chip selection l1 la_cs1# output with pull up frame bank a high portion chip selection l2 la_rw# output with pull up frame bank a read/write d18, b18, c18, a17, e17, b17, c17, e16, d17, b16, e15, c16, d16, d15, e14, c15, b15, e13, a15, d14, c14, d13, b14, a14, c13, e12, b13, a13, d12, c12, b12, a12, a11, e10, c10, b10, e9, a10, d11, d10, d8, d9, c9, b9, a9, c8, b8, a8, c7, e7, d7, b7, e8, a7, d6, c6, e6, b6, a6, a5, b5, c5, b4,a4 lb_d[63:0] i/o-ts with pull up fr ame bank b- data bit [63:0] d22, d20, e20, d21, a21, d19, b21, c21, a20, b20, e19, c20, a19, b19, e18, c19, a18 lb_a[19:3] output frame bank b - address bit [19:3] e21 lb_a[20] output with pull up frame bank b - address bit [20] d5 lb_clk output frame bank b clock input b11 lb_cs0# output with pull up fr ame bank b low portion chip selection e11 lb_cs1# output with pull up frame bank b high portion chip selection c11 lb_rw# output with pull up frame bank b read/write switch database interface e24,b27, d27, c27, a27, a28, b30, d28, e27, c30, d30, g26, e28, d29, e26, e29, h26, e30, j26, f30, f29, f28, f27, h27, g30, g29, k26, g27, g28, h30, h29, m27 b_d[31:0] output with pull up switch database domain - data bit [31:0] c22, b22, a22, e22, c23, b23, a23, c24, d24, d23, b24, a24, e23, c25, c26, b25, a25 b_a[18:2] output switch database address (512k) - address bit [18:2] c29 b_clk output switch database clock input d25 b_adsc# output with pull up swit ch database address status control b26 b_we# output with pull up switch database write chip select a26 b_oe# output with pull up switch database read chip select ball no(s) symbol i/o description
mvtx2804 data sheet 144 zarlink semiconductor inc. mii management interface aj16 m_mdc output mii management data clock - (common for all mii ports [7:0]) ag18 m_mdio i/o-ts with pull up mii management data i/o - (common for all mii ports -[7:0])) 2.5mhz ball no(s) symbol i/o description gmii / mii interface (193) gigabit ethernet access port ad29, ak30, aj22, ag17, aj11, aj6, af3,aa4 gref_clk [7:0] input w/ pul l up gigabit reference clock ak15 cm_clk input w/ pull up commo n clock shared by port g[7:0] af17 ind/cm input w/ pull up 1: select gref_clk[7:0] as clock 0: select cm_clk as clock for all ports aa30, ak29, ag25, ak18, aj13, ah7, ah3, ab1 mii tx clk[7:0] input w/ pull up v26, w29, w30, y28, w26, y29, w27, y30 ab26, ae27, ae28, ac27, ae29, ac26, ae30, ad26 ak27, ah27, af26, aj27, ah26, ak25, ag26, aj25 ag22, ag21, ag20, af22, ak21, ak20, af21, aj20 ag16, af16, ag15, af18, af15, ah15, aj15, ag14 ag11, aj10, af11, af10, ag9, af9, ah9, aj9 af6, aj5, af5, ag6, ak4, af4, ak3, ah4 af1, ac5, ae1, ae2, ae3, ac4, ae4, ad1 g7_rxd[7:0] g6_rxd[7:0] g5_rxd[7:0] g4_rxd[7:0] g3_rxd[7:0] g2_rxd[7:0] g1_rxd[7:0] g0_rxd[7:0] input w/ pull up g[7 :0] port - receive data bit [7:0] w28, ad30, ak28, ah22, ah16, ah10, ak5, ad5 g[7:0]_rx_dv input w/ pull down g[7:0]port - receive data valid v27, ad27, aj28, ah23, af19, ag12, ak6, af2 g[7:0]_rx_er input w/ pull up g[7:0]port - receive error ball no(s) symbol i/o description
mvtx2804 data sheet 145 zarlink semiconductor inc. ac30, aj29, ag23, ak16, ak11, ah6, ag3, y4 g[7:0]_crs/link input w/ pull down g[7:0]port - carrier sense aa28, af29, aj26, aj21, af14, ak10, aj4, ad3 g[7:0]_col input w/ pull up g[7 :0]port - collision detected aa29, af27, ak26, ah21, ah14, ag10, ah5, ac1 g[7:0]_rxclk input w/ pull up g[7:0]port - receive clock ab28, y26, ab29, ab30, aa27, ac28, ac29, aa26 ae26, af28, ag30, ag28, ag27, ah29, ah28, aj30 ak24, aj24, ag24, af24, ah24, af23, ak23, aj23 aj19, ah19, aj18, ah18, af20, ak17, ag19, aj17 ak14, af13, ah13, ak13, ah12, aj12, af12, ak12 af8, aj8, ak8, ag7, ag8, aj7, ak7, af7 ag4, ak1, aj1, aj2, ah2, ah1, ag1, ae5 aa5, ad4, ac2, y5, ac3, ab2, w5, ab3 g7_txd[7:0] g6_txd[7:0] g5_txd[7:0] g4_txd[7:0] g3_txd[7:0] g2_txd[7:0] g1_txd[7:0] g0_txd[7:0] output g[7:0]port - tran smit data bit [7:0] y27, ag29, ah25, ak19, ag13, ah8, ak2, ad2 g[7:0]_tx_en output w/ pull up g[7 :0]port - transmit data enable ab27, af30, af25, ah20, aj14, ak9, aj3, ab5 g[7:0]_tx_er output w/ pull up g[7:0]port - transmit error ad28, ah30, ak22, ah17, ah11, ag5, ag2, ab4 g[7:0]_ txclk output g[7:0]por t - gigabit transmit clock pma interface (193) gigabit ethernet access port (pcs) ad29, ak30, aj22, ag17, aj11, aj6, af3,aa4 gref_clk [7:0] input w/ pul l up gigabit reference clock ak15 cm_clk input w/ pull up commo n clock shared by port g[7:0] af17 ind/cm input w/ pull up 1: select gref_clk[7:0] as clock 0: select cm_clk as clock for all port ball no(s) symbol i/o description
mvtx2804 data sheet 146 zarlink semiconductor inc. v26, w29, w30, y28, w26, y29, w27, y30 ab26, ae27, ae28, ac27, ae29, ac26, ae30, ad26 ak27, ah27, af26, aj27, ah26, ak25, ag26, aj25 ag22, ag21, ag20, af22, ak21, ak20, af21, aj20 ag16, af16, ag15, af18, af15, ah15, aj15, ag14 ag11, aj10, af11, af10, ag9, af9, ah9, aj9 af6, aj5, af5, ag6, ak4, af4, ak3, ah4 af1, ac5, ae1, ae2, ae3, ac4, ae4, ad1 g7_rxd[7:0] \ g6_rxd[7:0] g5_rxd[7:0] g4_rxd[7:0] g3_rxd[7:0] g2_rxd[7:0] g1_rxd[7:0] g0_rxd[7:0] input w/ pull up g[7:0]port - pma receive data bit [7:0] w28, ad30, ak28, ah22, ah16, ah10, ak5, ad5 g[7:0]_rx_d[8] input w/ pull down g[7:0 ]port - pma receive data bit [8] v27, ad27, aj28, ah23, af19, ag12, ak6, af2 g[7:0]_rx_d[9] input w/ pull up g[7:0 ]port - pma receive data bit [9] aa28, af29, aj26, aj21, af14, ak10, aj4, ad3 g[7:0]_rxclk1 input w/ pull up g[7:0]port - pma receive clock 1 aa29, af27, ak26, ah21, ah14, ag10, ah5, ac1 g[7:0]_rxclk0 input w/ pull up g[7:0]port - pma receive clock 0 ball no(s) symbol i/o description
mvtx2804 data sheet 147 zarlink semiconductor inc. ab28, y26, ab29, ab30, aa27, ac28, ac29, aa26 ae26, af28, ag30, ag28, ag27, ah29, ah28, aj30 ak24, aj24, ag24, af24, ah24, af23, ak23, aj23 aj19, ah19, aj18, ah18, af20, ak17, ag19, aj17 ak14, af13, ah13, ak13, ah12, aj12, af12, ak12 af8, aj8, ak8, ag7, ag8, aj7, ak7, af7 ag4, ak1, aj1, aj2, ah2, ah1, ag1, ae5 aa5, ad4, ac2, y5, ac3, ab2, w5, ab3 g7_txd[7:0] g6_txd[7:0] g5_txd[7:0] g4_txd[7:0] g3_txd[7:0] g2_txd[7:0] g1_txd[7:0] g0_txd[7:0] output g[7:0]port - pma tr ansmit data bit [7:0] y27, ag29, ah25, ak19, ag13, ah8, ak2, ad2 g[7:0]_txd[8] output w/ pull up g[7:0]port - pma transmit data bit [8] ab27, af30, af25, ah20, aj14, ak9, aj3, ab5 g[7:0]_tx_d[9] output w/ pull up g[7:0 ]port - pma transmit data bit [9] ad28, ah30, ak22, ah17, ah11, ag5, ag2, ab4 g[7:0]_ txclk output g[7:0]port - pma gigabit transmit clock test facility (3) u29 t_mode0 i/o-ts with pull up test - set upon reset, and provides nand tree test output during test mode. use external pull up for normal operation u28 t_mode1 i/o-ts with pull up test - set upon reset, and provides nand tree test output during test mode. use external pull up for normal operation a3 scan_en input w/ pull down enable test mode. for normal operation leave it open led interface (serial and parallel) r28, t26, r27, t27, u27, t28, t29, t30 t_d[7:0]/ led_pd[7:0] output while resetting, t_d[7,0] are in input mode and are used as strapping pins. internal pullup led_pd - parallel led data [7:0] ball no(s) symbol i/o description
mvtx2804 data sheet 148 zarlink semiconductor inc. p26, p30, p29, p28, p27, r26, r30, r29 t_d[15:8]/ led_pt[7:0] output while resetting, t_d[15:8] are in input mode and are used as strapping pins. internal pullup led_pr[7:0] - parallel led port sel [7:0] v29 led_clk0/ led_pt[8] output led_clk0 - led serial interface output clock led_pt[8] - parallel led port sel [8] v30 led_blink/ led_do/ led_pt[9] output while resetting, led-blink is in input mode and is used as strapping pin. 1: no blink, 0: blink. internal pullup. led_do - led serial data output stream led_pt[9] - parallel led port sel [9] v28 led_pm/ led_synco# output w/ pull up while resett ing, led_pm is in input mode and is used as strapping pin. internal pull up. 1: enable parallel interface, 0: enable serial interface. led_synco# - led output data stream envelop system clock, power, and ground pins a16 s_clk input system clock at 133 mhz u26 s_rst# input - st reset input u30 resout# output reset phy b1 dev_cfg[0] input w/ pull down not used b28 dev_cfg[1] input w/ pull down not used ae7, ae9, f10, f21, f22, f9, g25, g6, j25, j6, k25, k6, aa25, aa6, ab25, ab6, ad25, ae10, ae21, ae22 vdd power core +2.5 volt dc supply v14, v15, v16, v17, v18, f16, f24, f25, f6, f7, n13, n14, n15, n16, n17, n18, p13, p14, p15, p16, p17, p18, r13, r14, r15, r16, r17, r18, r25, r6, t13, t14, t15, t16, t17, t18, t25, t6, u13, u14, u15, u16, u17, u18, v13, ad6, ae15, ae16, ae24, ae25, ae6, f15 vss ground ground a1, c28 avdd power analog +2.5 volt dc supply e5, e25 avss ground analog ground ball no(s) symbol i/o description
mvtx2804 data sheet 149 zarlink semiconductor inc. ae12, ae13, ae14, ae17, ae18, ae19, f12, f13, f14, f17, f18, f19, m25, m6, n25, n6, p25, p6, u25, u6, v25, v6, w25, w6 vcc power i/o +3.3 volt dc supply bootstrap pins (default= pull up, 1= pull up 0= pull down) ad2,ab5 g0_tx_en g0_tx_er default: pcs giga0 mode: g0_txen g0_txer 0 0 mii 0 1 rsvd 1 0 gmii 1 1 pcs ak2,aj3 g1_tx_en g1_txer default: pcs giga1 mode: g1_txen g1_txer 0 0 mii 0 1 rsvd 1 0 gmii 1 1 pcs ah8,ak9 g2_tx_en g2_tx_er default: pcs giga2 mode: g2_txen g2_txer 0 0 mii 0 1 rsvd 1 0 gmii 1 1 pcs ag13,aj14 g3_tx_en g3_tx_er default: pcs giga3 mode: g3_txen g3_txer 0 0 mii 0 1 rsvd 1 0 gmii 1 1 pcs ak19,ah20 g4_tx_en g4_tx_er default: pcs giga4 mode: g4_txen g4_txer 0 0 mii 0 1 rsvd 1 0 gmii 1 1 pcs ah25,af25 g5_tx_en g5_tx_er default: pcs giga5 mode: g5_txen g5_txer 0 0 mii 0 1 rsvd 1 0 gmii 1 1 pcs ag29,af30 g6_tx_en g6_tx_er default: pcs giga6 mode: g6_txen g6_txer 0 0 mii 0 1 rsvd 1 0 gmii 1 1 pcs ball no(s) symbol i/o description
mvtx2804 data sheet 150 zarlink semiconductor inc. y27,ab27 g7_tx_en g7_tx_er default: pcs giga7 mode: g7_txen g7_txer 0 0 mii 0 1 rsvd 1 0 gmii 1 1 pcs after reset t_d[15:0] are used by the led interface t30 t_d[0] 1 giga link active status 0 - active low 1 - active high t29 t_d[1] 1 power saving 0 - no power saving 1 - power saving stop mac clock if no mac activity. t28 t_d[2] must be pulled-down reserved - must be pulled-down u27 t_d[3] 1 hot plug port module detection enable 0 - module detection enable 1 - module detection disable t27 t_d[4] must be pulled-down reserved - must be pulled-down r27 t_d[5] 1 sram memory size 0 - 512k sram 1 - 256k sram t26 t_d[6] 1 cpu port mode 0 ? 8 bit cpu data bus 1 ? 16 bit cpu data bus r28 t_d[7] 1 fdb memory depth 1- one memory layer 0 - two memory layers w4, e21 la_a[20], lb_a[20] 1 fdb memory size 11 - 2m per bank = 4m total 10 - 1m per bank = 2m total 0x - 512k per bank = 1m total r29 t_d[8] 1 eeprom installed 0 - eeprom is installed 1 - eeprom is not installed r30 t_d[9] 1 mct aging enable 0 - mct aging disable 1 - mct aging enable r26 t_d[10] 1 fcb handle aging enable 0 - fcb handle aging disable 1 - fcb handle aging enable p27 t_d[11] 1 timeout reset enable 0 - timeout reset disable 1 - timeout reset enable issue reset if any state machine did not go back to idle for 5sec. p28, p29 t_d[13:12] 1 reserved ball no(s) symbol i/o description
mvtx2804 data sheet 151 zarlink semiconductor inc. notes: # = active low signal input = input signal in-st = input signal with schmitt-trigger output = output signal (tri-state driver) out-od = output signal with open-drain driver i/o-ts = input & output signal with tri-state driver i/o-od = input & output signal with open-drain driver p30 t_d[14] 1 cpu installed 0 - cpu installed 1 - cpu is not installed p26 t_d[15] 1 external ram test 0 - perform the infinite loop of zbt ram bist. debug test only 1 - regular operation. n30, n29, n28 p_d[2:0] 111 zbt ram la_clk turning 3'b000 - control by reg. lclkcr[2:0] 3'b001 - delay by method # 0 3'b010 - delay by method # 1 3'b011 - delay by method # 2 3'b100 - delay by method # 3 3'b101 - delay by method # 4 3'b110 - delay by method # 5 3'b111 - delay by method # 6 - use this method m30, m29, m28 p_d[5:3]1 zbt ram lb_clk turning 3'b000 - control by reg. lclkcr[6:4] 3'b001 - delay by method # 0 3'b010 - delay by method # 1 3'b011 - delay by method # 2 3'b100 - delay by method # 3 3'b101 - delay by method # 4 3'b110 - delay by method # 5 3'b111 - delay by method # 6 - use this method l29, l28, n26 p_d[8:6] 111 sbram b_clk turning 3'b000 - control by bclkcr[2:0] 3'b001 - delay by method # 0 3'b010 - delay by method # 1 3'b011 - delay by method # 2 3'b100 - delay by method # 3 3'b101 - delay by method # 4 3'b110 - delay by method # 5 3'b111 - delay by method # 6- use this method ball no(s) symbol i/o description
mvtx2804 data sheet 152 zarlink semiconductor inc. 12.3 ball signal name ball no. signal name a1 avcc b1 dev_cfg[0] b2 la_d[0] c2 la_clk c1 la_d[1] d1 la_d[2] c3 la_d[3] e4 la_d[4] d2 la_d[5] e3 la_d[6] e2 la_d[7] e1 la_d[8] d3 la_d[9] f1 la_d[10] f2 la_d[11] f3 la_d[12] f4 la_d[13] f5 la_d[14] g1 la_d[15] g2 la_d[16] g5 la_d[17] g4 la_d[18] g3 la_d[19] h1 la_d[20] h2 la_d[21] h3 la_d[22] j1 la_d[23] h5 la_d[24] j2 la_d[25] j3 la_d[26] j4 la_d[27] k1 la_d[28] h4 la_d[29] k2 la_d[30] m1 la_d[34] m2 la_d[35] m3 la_d[36] k4 la_d[37] n1 la_d[38] p5 la_d[39] n2 la_d[40] l5 la_d[41] n3 la_d[42] p1 la_d[43] p2 la_d[44] p3 la_d[45] l4 la_d[46] r5 la_d[47] m5 la_d[48] r1 la_d[49] r2 la_d[50] r3 la_d[51] r4 la_d[52] m4 la_d[53] t4 la_d[54] t3 la_d[55] n5 la_d[56] t2 la_d[57] t1 la_d[58] u4 la_d[59] u3 la_d[60] n4 la_d[61] u2 la_d[62] u1 la_d[63] v3 la_a[3] p4 la_a[4] v2 la_a[5] v1 la_a[6] y2 la_a[13] v4 la_a[14] y1 la_a[15] v4 la_a[14] y1 la_a[15] aa3 la_a[16] aa2 la_a[17] v5 la_a[18] aa1 la_a[19] ball no. signal name w4 la_a[20] y4 g0_crs/lnk aa4 gref_clk[0] ab4 g0_txclk ab3 g0_txd[0] w5 g0_txd[1] ab2 g0_txd[2] ab1 mii_tx_clk[0] ac3 g0_txd[3] y5 g0_txd[4] ac2 g0_txd[5] ac1 g0_rxclk ad3 g0_col ad4 g0_txd[6] aa5 g0_txd[7] ad2 g0_tx_en ab5 g0_tx_er ad1 g0_rxd[0] ae4 g0_rxd[1] ac4 g0_rxd[2] ae3 g0_rxd[3] ae2 g0_rxd[4] ae1 g0_rxd[5] ac5 g0_rxd[6] af1 g0_rxd[7] ad5 g0_rx_dv af2 g0_rx_er j5 la_d[31] k3 la_cs0# l1 la_cs1# l2 la_rw# l3 la_d[32] k5 la_d[33] ah2 g1_txd[3] aj2 g1_txd[4] aj1 g1_txd[5] ak1 g1_txd[6] ag4 g1_txd[7] ak2 g1_tx_en ball no. signal name
mvtx2804 data sheet 153 zarlink semiconductor inc. ah3 mii_tx_clk[1] aj3 g1_tx_er ah4 g1_rxd[0] ak3 g1_rxd[1] af4 g1_rxd[2] ak4 g1_rxd[3] ah5 g1_rxclk aj4 g1_col ag6 g1_rxd[4] af5 g1_rxd[5] aj5 g1_rxd[6] af6 g1_rxd[7] ak5 g1_rx_dv ak6 g1_rx_er aj6 gref_clk[2] ag5 g2_txclk ah6 g2_crs/lkink af7 g2_txd[0] ak7 g2_txd[1] aj7 g2_txd[2] ag8 g2_txd[3] ag7 g2_txd[4] ah7 mii_tx_clk[2] ak8 g2_txd[5] aj8 g2_txd[6] t5 la_a[7] w3 la_a[8] w2 la_a[9] w1 la_a[10] u5 la_a[11] y3 la_a[12] ag10 g2_rxclk ak10 g2_col aj10 g2_rxd[6] ag11 g2_rxd[7] ah10 g2_rx_dv ag12 g2_rx_er ak11 g3_crs/link aj11 gref_clk[3] ball no. signal name ah11 g3_txclk ak12 g3_txd[0] af12 g3_txd[1] aj12 g3_txd[2] ah12 g3_txd[3] ak13 g3_txd[4] aj13 mii_tx_clk[3] ah13 g3_txd[5] af13 g3_txd[6] ak14 g3_txd[7] ag13 g3_tx_en aj14 g3_tx_er ah14 g3_rxclk af14 g3_col ag14 g3_rxd[0] ak15 cm_clk af17 ind_cm aj15 g3_rxd[1] ah15 g3_rxd[2] af15 g3_rxd[3] af18 g3_rxd[4] ag15 g3_rxd[5] af16 g3_rxd[6] af3 gref_clk[1] ag2 g1_txclk ag3 g1_crs/link ae5 g1_txd[0] ag1 g1_txd[1] ah1 g1_txd[2] ag19 g4_txd[1] ak17 g4_txd[2] af20 g4_txd[3] ah18 g4_txd[4] aj18 g4_txd[5] ak18 mii_tx_clk[4] ah19 g4_txd[6] aj19 g4_txd[7] ak19 g4_tx_en ah20 g4_tx_er ball no. signal name aj20 g4_rxd[0] af21 g4_rxd[1] ak20 g4_rxf[2] ah21 g4_rxclk aj21 g4_col ak21 g4_rxd[3] af22 gr_rxd[4] ag20 g4_rxd[5] ag21 g4_rxd[6] ag22 g4_rxd[7] ah22 g4_rx_dv aj22 gref_clk[5] ak22 g5_txclk ah23 g4_rx_er ag23 g5_crs/link aj23 g5_txd[0] ak23 g5_txd[1] af23 g5_txd[2] ah24 g5_txd[3] af24 g5_txd[4] ag24 g5_txd[5] af8 g2_txd[7] ah8 g2_tx_en ak9 g2_tx_er aj9 g2_rxd[0] ah9 g2_rxd[1] af9 g2_rxd[2] ag9 g2_rxd[3] af10 g2_rxd[4] af11 g2_rxd[5] aj26 g5_col ah26 g5_rxd[3] aj27 g5_rxd[4] af26 g5_rxd[5] ah27 g5_rxd[6] ak27 g5_rxd[7] ak28 g5_rx_dv aj28 g5_rx_er aj29 g6_crs/link ball no. signal name
mvtx2804 data sheet 154 zarlink semiconductor inc. ak29 mii_tx_clk[6] ak30 gref_clk[6] ah28 g6_txd[1] ah29 g6_txd[2] ag27 g6_txd[3] ag28 g6_txd[4] ah30 g6_txclk ag30 g6_txd[5] af28 g6_txd[6] ae26 g6_txd[7] ag29 g6_tx-en af27 g6_rxclk af29 g6_col af30 g6_tx_er ad26 g6_rxd[0] ae30 g6_rxd[1] ac26 g6_rxd[2] ae29 g6_rxd[3] ac27 g6_rxd[4] ag16 g3_rxd[7] ah16 g3_rx_dv af19 g3_rx_er aj16 m_mdc ag18 m_mdio ak16 g4_crs/link ag17 gref_clk[4] ah17 g4_txclk aj17 g4_txd[0] aa27 g7_txd[3] ab30 g7_txd[4] ab29 g7_txd[5] y26 g7_txd[6] ab28 g7_txd[7] y27 g7_tx_en ab27 g7_tx_er aa30 mii_tx_clk[7] aa29 g7_rxclk aa29 c7_col y30 g7_rxd[0] ball no. signal name w27 g7_rxd[1] y29 g7_rxd{2] w26 g7_rxd{3] y28 g7_rxd{4] w30 g7_rxd{5] w29 g7_rxd{6] v26 g7_rxd{7] w28 g7_rx_dv v27 g7_rx_er v30 led_do v29 led_clk0 v28 led_synco# u26 s_rst# u30 resout# u29 t_mode{0} u28 t_mode{1] t30 t_d[0] t29 t_d[1] aj24 g5_txd[6] ak24 g5_txd[7] ag25 mii_tx_clk[5] ah25 g5_tx_en af25 g5_tx_er aj25 g5_rxd[0]] ag26 g5_rxd[1] ak25 g5_rxd[2] ak26 g5_rxclk p29 t_d[13] p30 t_d[14] p26 t_d[15] n28 p_d[0] n29 p_d[1] n30 p_d[2] m28 p_d[3] m29 p_d[4] m30 p_d[5] n26 p_d[6] l28 p_d[7] l29 p_d[8] ball no. signal name n27 p_d[9] l30 p_d[10] k28 p_d[11] k29 p_d[12] k30 p_d[13] l27 p_d[14] k27 p_d[15] m26 p_a[0] j27 p_a[1] j28 p_a[2] j29 p_we# j30 p_rd# l26 p_cs# h28 p_int# m27 b_d[0] h29 b_d[1] h30 b_d[2] ae28 g6_rxd[5] ae27 g6_rxd[6] ab26 g6_rxd[7] ad30 g6_rx_dv ad29 gref_clk[7] ad27 g6_rx_er ad28 g7_txclk ac30 g7_crs/link aa26 g7_txd[0] ac29 g7_txd[1] ac28 g7_txd[2] e30 b_d[14] h26 b_d[15] e29 b_d[16] e26 b_d[17] d29 b_d[18] e28 b_d[19] g26 b_d[20] d30 b_d[21] c30 b_d[22] e27 b_d[23] c29 b_clk ball no. signal name
mvtx2804 data sheet 155 zarlink semiconductor inc. d28 b_d[24] b30 b_d[25] f26 nc1 d26 nc2 a30 nc3 a29 nc4 b29 nc5 e25 agnd b28 dev_cfg[1] c28 avdd a28 b_d[26] a27 b_d[27] c27 b_d[28] d27 b_d[29] b27 b_d[30] t28 t_d[2] u27 t_d[3] t27 t_d[4] r27 t_d[5] t26 t_d[6] r28 t_d[7] r29 t_d[8] r30 t_d[9] r26 t_d[10] p27 t_d[11] p28 t_d[12] a23 b_a[12] b23 b_a[13] c23 b_a[14] e22 b_a[15] a22 b_a[16] b22 b_a[17] c22 b_a[18] e21 lb_a[20] d22 lb_a[19] d20 lb_a[18] e20 lb_a[17] d21 lb_a[16] a21 lb_a[15] ball no. signal name d19 lb_a[14] b21 lb_a[13] c21 lb_a[12] a20 lb_a[11] b20 lb_a[10] e19 lb_a[9] c20 lb_a[8] a19 lb_a[7] b19 lb_a[6] e18 lb_a[5] c19 lb_a[4] a18 lb_a[3] d18 lb_d[63] g28 b_d[3] g27 b_d[4] k26 b_d[5] g29 b_d[6] g30 b_d[7] h27 b_d[8] f27 b_d[9] f28 b_d[10] f29 b_d[11] f30 b_d[12] j26 b_d[13] e14 lb_d[49] c15 lb_d[48] b15 lb_d[47] e13 lb_d[46] a15 lb_d[45] d14 lb_d[44] c14 lb_d[43] d13 lb_d[42] b14 lb_d[41] a14 lb_d[40] c13 lb_d[39] e12 lb_d[38] b13 lb_d[37] a13 lb_d[36] d12 lb_d[35] ball no. signal name c12 lb_d[34] b12 lb_d[33] a12 lb_d[32] c11 lb_rw# e11 lb_cs1# b11 lb_cs0# a11 lb_d[31] e10 lb_d[30] c10 lb_d[29] b10 lb_d[28] e9 lb_d[27] e24 b_d[31] d25 b_adsc# b26 b_we# a26 b_oe# a25 b_a[2] b25 b_a[3] c26 b_a[4] c25 b_a[5] e23 b_a[6] a24 b_a[7] b24 b_a[8] d23 b_a[9] d24 b_a[10] c24 b_a[11] b7 lb_d[12] e8 lb_d[11] a7 lb_d[10] d6 lb_d[9] c6 lb_d[8] e6 lb_d[7] b6 lb_d[6] a6 lb_d[5] a5 lb_d[4] b5 lb_d[3] c5 lb_d[2] b4 lb_d[1] d5 lb_clk a4 lb_d[0] ball no. signal name
mvtx2804 data sheet 156 zarlink semiconductor inc. a3 scan_en e5 agnd c4 nc6 b3 nc7 d4 nc8 a2 nc9 ad6 vss ae15 vss ae16 vss ae24 vss b18 lb_d[62] c18 lb_d[61] a17 lb_d[60] e17 lb_d[59] b17 lb_d[58] c17 lb_d[57] e16 lb_d[56] d17 lb_d[55] a16 s_clk b16 lb_d[54] e15 lb_d[53] c16 lb_d[52] d16 lb_d[51] d15 lb_d[50] p15 vss p16 vss p17 vss p18 vss r13 vss r14 vss r15 vss r16 vss r17 vss r18 vss r25 vss r26 vss t13 vss t14 vss t15 vss ball no. signal name t16 vss t17 vss t18 vss t25 vss t6 vss u13 vss u14 vss u15 vss u16 vss a10 lb_d[26] d11 lb_d[25] d10 lb_d[24] d8 lb_d[23] d9 lb_d[22] c9 lb_d[21] b9 lb_d[20] a9 lb_d[19] c8 lb_d[18] b8 lb_d[17] a8 lb_d[16] c7 lb_d[15] e7 lb_d[14] d7 lb_d[13] ae7 vdd ae9 vdd f10 vdd f21 vdd f22 vdd f9 vdd g25 vdd g6 vdd j25 vdd j6 vdd k25 vdd k6 vdd ae12 vcc ae13 vcc ae14 vcc ae17 vcc ball no. signal name ae18 vcc ae19 vcc f12 vcc f13 vcc f14 vcc f17 vcc f18 vcc f19 vcc ae25 vss ae6 vss f15 vss f16 vss f24 vss f25 vss f6 vss f7 vss n13 vss n14 vss n15 vss n16 vss n17 vss n18 vss p13 vss p14 vss u17 vss u18 vss v13 vss v14 vss v15 vss v16 vss v17 vss v18 vss aa25 vdd aa6 vdd ab25 vdd ab6 vdd ad25 vdd ae10 vdd ae21 vdd ball no. signal name
mvtx2804 data sheet 157 zarlink semiconductor inc. ae22 vdd m25 vcc m6 vcc n25 vcc n6 vcc p25 vcc u25 vcc u6 vcc v6 vcc w25 vcc w6 vcc ball no. signal name
mvtx2804 data sheet 158 zarlink semiconductor inc. 12.4 characteristics and timing 12.4.1 absolute maximum ratings storage temperature -65c to +150c operating temperature -40c to +85c maximum junction temperature +125c supply voltage vcc with respect to v ss +3.0 v to +3.6 v supply voltage vdd with respect to v ss +2.38 v to +2.75 v voltage on input pins -0.5 v to (vcc + 3.3 v) caution : stress above those listed may damage the device. exposure to the absolute maximum ratings for extended periods may affect device reliability. functi onality at or above these limits is not implied. 12.4.2 dc electrical characteristics vcc = 3.0 v to 3.6 v (3.3v +/- 10%)t ambient = -40c to +85c vdd = 2.5v +10% -5%
mvtx2804 data sheet 159 zarlink semiconductor inc. 12.4.3 recommended operating conditions symbol parameter descr iption min type max unit f osc frequency of operation 133 mhz i cc supply current ? @ 133 mhz (3.3 v supply) 720 930 ma i dd supply current ? @ 133 mhz (2.5 v supply) 1400 1700 ma v oh output high voltage (cmos) 2.4 v v ol output low voltage (cmos) 0.4 v v ih-ttl input high voltage (ttl 5v tolerant) 2.0 vcc + 2.0 v v il-ttl input low voltage (ttl 5v tolerant) 0.8 v i il input leakage current (0.1 v < v in < vcc) (all pins except those with internal pull-up/pull-down resistors) 10 a i ol output leakage current (0.1 v < vout < vcc) 10 a c in input capacitance 5 pf c out output capacitance 5 pf c i/o i/o capacitance 7 pf ja thermal resistance with 0 air flow 11.2 c/w ja thermal resistance with 1 m/s air flow 9.9 c/w ja thermal resistance with 2 m/s air flow 8.7 c/w jc thermal resistance between junction and case 3.3 c/w
mvtx2804 data sheet 160 zarlink semiconductor inc. 12.5 ac characteristics and timing 12.5.1 typical reset & bootstrap timing diagram figure 8 - typical reset & bootstrap timing diagram symbol parameter min typ note: r1 delay until resout# is tri-stated 10ns resout# state is then determined by the external pull-up/down resistor r2 bootstrap stabilization 1 s10 s bootstrap pins sampled on rising edge of s_rst# 1 1. the t_d[15:0] pins will switch over to the led inte rface functionality in 3 sclk cycles after s_rst# goes high r3 resout# assertion 2ms table 5 - reset & bootstrap timing resout# tri-stated s_rst# r1 r2 r3 bootstrap pins inputs outputs outputs
mvtx2804 data sheet 161 zarlink semiconductor inc. 12.5.2 typical cpu timing diagram for a cpu write cycle figure 9 - typical cpu timing di agram for a cpu write cycle description (sclk=133mhz) write cycle symbol min (ns) max (ns) write set up time t ws 10 write active time t wa 15 at least 2 sclk write hold time t wh 2 write recovery time t wr 22.5 at least 3 sclk data set up time t ds 10 data hold time t dh 2 table 6 - cpu write cycle p_cs# p_we# data to vtx2600 p_addr t wr hold time addr0 t ws t wa at least 2 sclks set up time data 1 data 0 recovery time addr1 t wh t ws t wa at least 2 sclks t wh t dh t dh t ds t ds
mvtx2804 data sheet 162 zarlink semiconductor inc. 12.5.3 typical cpu timing diagram for a cpu read cycle figure 10 - typical cpu timing diagram for a cpu read cycle description (sclk=133mhz) read cycle symbol min (ns) max (ns) read set up time t rs 10 read active time t ra 15 at least 2 sclk read hold time t rh 2 read recovery time t rr 22.5 at least 3 sclk data valid time t ds 10 data inactive time t di 2 table 7 - cpu read cycle p_cs# p_rd# data to cpu p_addr t rr recovery time 2ns inactive time addr0 t rs t dv t ra at least 2 sclks valid time data 1 data 0 at least 3 sclks t di addr1 t rh t rs t ra at least 2 sclks t rh t di t dv
mvtx2804 data sheet 163 zarlink semiconductor inc. 12.5.4 local frame buffer zbt sram memory interface 12.5.4.1 local zbt sram memory interface a figure 11 - local memory interface ? input setup and hold timing figure 12 - local memory interface - output valid delay timing (sclk= 133mhz) symbol parameter min (ns) max (ns) note: l1 la_d[63:0] input set-up time 2.5 l2 la_d[63:0] input hold time 1 1 l3 la_d[63:0] output valid delay 3.0 5 2c l = 25pf l4 la_a[20:3] output valid delay 3.0 5 3c l = 30pf l6 la_cs[1:0]# output valid delay 3.0 5 4c l = 30pf l9 la_we# output valid delay 3.0 5 5c l = 25pf table 8 - ac characteristics ? local frame buffer zbt-sram memory interface a l1 l2 la_clk la_d[63:0] l3-min l3-max l4-min l4-max l6-min l6-max l9-min l9-max la_clk la_d[63:0] la_a[20:3] la_cs[1,0]# la_rw#
mvtx2804 data sheet 164 zarlink semiconductor inc. 12.5.4.2 local zbt sram memory interface b figure 13 - local memory interface ? input setup and hold timing figure 14 - local memory interface - output valid delay timing (sclk= 133mhz) symbol parameter min (ns) max (ns) note: l1 lb_d[63:0] input set-up time 2.5 l2 lb_d[63:0] input hold time 1 l3 lb_d[63:0] output valid delay 3.0 5 c l = 25pf l4 lb_a[20:3] output valid delay 3.0 5 c l = 30pf l6 lb_cs[1:0]# output valid delay 3.0 5 c l = 30pf l9 lb_we# output valid delay 3.0 5 c l = 25pf table 9 - ac characteristics ? local frame buffer zbt-sram memory interface b l1 l2 lb_clk lb_d[63:0] l3-min l3-max l4-min l4-max l6-min l6-max l9-min l9-max lb_clk lb_d[63:0] lb_a[20:3] lb_cs[1,0]# lb_rw#
mvtx2804 data sheet 165 zarlink semiconductor inc. 12.5.5 local switch database sbram memory interface 12.5.5.1 local s bram memory interface figure 15 - local memory interface ? input setup and hold timing figure 16 - local memory interface - output valid delay timing (sclk= 133mhz) symbol parameter min (ns) max (ns) note: l1 b_d[31:0] input set-up time 2.5 l2 b_d[31:0] input hold time 1 l3 b_d[31:0] output valid delay 3.0 5 c l = 25pf l4 b_a[18:2] output valid delay 3.0 5 c l = 30pf l6 b_adsc# output valid delay 3.0 5 c l = 30pf l10 b_we# output valid delay 3.0 5 c l = 25pf l11 b_oe# output valid delay 3.0 4 c l = 25pf table 10 - ac characteristics ? local switch database sbram memory interface l1 l2 b_clk b_d[31:0] l3-min l3-max l4-min l4-max l6-min l6-max l10-min l10-max l11-min l11-max b_clk b_d[31:0] b_a[18:2] b_adsc# b_we# b_oe#
mvtx2804 data sheet 166 zarlink semiconductor inc. 12.5.6 media independent interface figure 17 - ac characteristics ? media independent interface figure 18 - ac characteristics ? media independent interface (mii_txclk & g_rxclk = 25mhz) symbol parameter min (ns) max (ns) note: m2 g[7:0]_rxd[3:0] input setup time 4 m3 g[7:0]_rxd[3:0] input hold time 1 m4 g[7:0]_crs_dv input setup time 4 m5 g[7:0]_crs_dv input hold time 1 m6 g[7:0]_txen output delay time 3 11 c l = 20 pf m7 g[7:0]_txd[3:0] output delay time 3 11 c l = 20 pf table 11 - ac characteristics ? media independent interface m6-min m6-max m7-min m7-max mii_txclk[7:0] g[7:0]_txen g[7:0] _txd[3:0] m2 g[7:0]_rxclk g[7:0]_rxd[3:0] g[7:0]_crs_dv m3 m4 m5
mvtx2804 data sheet 167 zarlink semiconductor inc. 12.5.7 gigabit media independent interface figure 19 - ac characteristics - gmii figure 20 - ac characteristics ? gi gabit media independent interface (g_rclk & g_refclk = 125mhz) symbol parameter min (ns) max (ns) note: g1 g[7:0]_rxd[7:0] input setup times 2 g2 g[7:0]_rxd[7:0] input hold times 1 g3 g[7:0]_rx_dv input setup times 2 g4 g[7:0]_rx_dv input hold times 1 g5 g[7:0]_rx_er input setup times 2 g6 g[7:0]_rx_er input hold times 1 g7 g[7:0]_crs input setup times 2 g8 g[7:0]_crs input hold times 1 table 12 - ac characteristics ? gigabit media independent interface g12-min g12-max g13-min g13-max g14-min g14-max g[7:0]_txclk g[7:0]_txd[7:0] [15:0] g[7:0]_tx_en g[7:0]_tx_er g[7:0]_rxd[7:0] g[7:0}_rx_dv g[7:0]_rx_er g[7:0]_rx_crs g1 g3 g5 g7 g2 g4 g6 g8 g[7:0]_rxclk
mvtx2804 data sheet 168 zarlink semiconductor inc. 12.5.8 pcs interface figure 21 - ac characteristics ? pcs interface figure 22 - ac characteristics ? pcs interface g12 g[7:0]_txd[7:0] output delay times 1.5 5 c l = 20pf g13 g[7:0]_tx_en output delay times 2 5 c l = 20pf g14 g[7:0]_tx_er output delay times 1 5 c l = 20pf (g_rclk & g_refclk = 125mhz) symbol parameter min (ns) max (ns) note: g21 g[7:0]_rxd[9:0] input se tup times ref to g_rxclk 2 g22 g[7:0]_rxd[9:0] input ho ld times ref to g_rxclk 1 table 13 - ac characteristics ? pcs interface (g_rclk & g_refclk = 125mhz) symbol parameter min (ns) max (ns) note: table 12 - ac characteristics ? gigabit media independent interface (continued) g30-min g30-max g[7:0]_txclk g[7:0]_txd[9:0] [15:0]
mvtx2804 data sheet 169 zarlink semiconductor inc. 12.5.9 led interface figure 23 - ac characteristics ? led interface g23 g[7:0]_rxd[9:0] input setup times ref to g_rxclk1 2 g24 g[7:0]_rxd[9:0] input ho ld times ref to g_rxclk1 1 g25 g[7:0]_crs input setup times 2 g26 g[7:0]_crs input hold times 1 g30 g[7:0]_txd[9:0] output delay times 1 5 c l = 20pf variable freq. symbol parameter min (ns) max (ns) note: le5 led_syn output valid delay 1 7 c l = 30pf le6 led_bit output valid delay 1 7 c l = 30pf table 14 - ac characteristics ? led interface (g_rclk & g_refclk = 125mhz) symbol parameter min (ns) max (ns) note: table 13 - ac characteristics ? pcs interface (continued) le5-min le5-max le6-min le6-max led_clk led_syn led_bit
mvtx2804 data sheet 170 zarlink semiconductor inc. 12.5.10 mdio input setup and hold timing figure 24 - mdio input setup and hold timing figure 25 - mdio output delay timing 1mhz symbol parameter min (ns) max (ns) note: d1 mdio input setup time 10 d2 mdio input hold time 2 d3 mdio output delay time 1 20 c l = 50pf table 15 - mdio timing mdc d1 d2 mdio d3-min d3-max mdc mdio
mvtx2804 data sheet 171 zarlink semiconductor inc. 12.5.11 i 2 c input setup timing figure 26 - i 2 c input setup timing figure 27 - i 2 c output delay timing 500khz symbol parameter min (ns) max (ns) note: s1 sda input setup time 20 s2 sda input hold time 1 s3* sda output delay time 1 20 c l = 30pf * open drain output. low to high transistor is controlled by external pullup resistor. table 16 - i 2 c timing scl s1 s2 sda s3-min s3-max scl sda
mvtx2804 data sheet 172 zarlink semiconductor inc. 12.5.12 serial interface setup timing figure 28 - serial interface setup timing figure 29 - serial interface output delay timing (sclk =133 mhz) symbol parameter min (ns) max (ns) note: d1 ps_di setup time 20 d2 ps_di hold time 10 d3 ps_do output delay time 1 50 c l = 100pf d4 strobe low time 5 s d5 strobe high time 5 s table 17 - serial interface timing strobe d1 d2 ps_di d1 d2 d4 d5 d3-min d3-max strobe ps_do
apprd. issue date acn package code previous package codes: conforms to jedec ms - 034 e b e e1 a2 d d1 a a1 40.20 39.80 34.50 ref 596 1.27 0.60 0.90 34.50 ref 1.17 ref 39.80 min 0.50 2.20 40.20 2.46 0.70 max 6. substrate thickness is 0.56 mm 4. n is the number of solder balls 2. dimension "b" is measured at the maximum solder ball diameter 1. controlling dimensions are in mm 5. not to scale. note: d e e1 d1 e a a1 a2 b 3. seating plane is defined by the spherical crowns of the solder balls.
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